The Network Locating Principle in Flexible Circuit Board Assembly

Author(s):  
Ruijun Chen

This paper focuses on developing the Network Locating Principle for fixturing tooling design in flexible circuit board assembly. From a viewpoint of Thermodynamics, a flexible circuit board populated with electronic components on the first side is a closed thermodynamic system. It experiences deformation energy change, assembly load work, and heat transfer during an isothermal assembly process on the second side, such as solder paste deposit printing and electronic component placement processes. Based on the First and Second Laws of Thermodynamics and Energy Equation of Thermoelastic Theory, a fixturing analysis is developed to investigate the deformation energy change, and furthermore the theoretical fixturing solution is derived to minimize the assembly load work during the isothermal assembly processes. To this end, the Network Locating Principle is proposed to guide fixturing tooling design for the isothermal assembly processes on the second side. Effectiveness of the Network Locating Principle is verified in numerical and experimental studies of flip chip placement processes on a thin flexible circuit.

2015 ◽  
Vol 2015 (1) ◽  
pp. 000827-000832
Author(s):  
Brandon Judd ◽  
Maria Durham

The use of bottom terminated components (BTCs) such as quad-flat no-leads (QFNs) has become commonplace in the circuit board assembly world. This package offers several benefits including its small form factor, its excellent thermal and electrical performance, easy PCB trace routing, and reduced lead inductance. These components are generally attached to PWBs PCBs via solder paste. The design of these components with the large thermal pad, along with the tendency of solder paste to outgas during reflow from the volatiles in the flux, creates a difficult challenge in terms of voiding control within the solder joint. Voiding can have a serious effect on the performance of these components, including the mechanical properties of the joint as well as spot overheating. Solder preforms with a flux coating can be added to the solder paste to help reduce voiding. This study will focus on the benefits of utilizing solder preforms with modern flux coatings in conjunction with solder paste to help reduce voiding under QFNs, as well as the design and process parameters which provide optimal results.


2018 ◽  
Vol 2018 (1) ◽  
pp. 000393-000402
Author(s):  
Thomas F. Marinis ◽  
Joseph W. Soucy

Abstract The cost of optoelectronic assemblies is significantly higher than that of electronic assemblies due in large part to the method of assembly. A typical computer circuit board is built by screen printing solder paste onto a printed wiring board, placing components on the board at rates of several thousand per hour, and then reflowing the solder paste in a conveyor oven. By contrast, optoelectronic assemblies are built up in a sequential process in which epoxy is dispensed for a single component, which is placed and held in position until the epoxy is cured. Many minutes are required to build an optoelectronic assembly, such as a laser module, by this approach, also the precision robotic placement tool needed for this process costs in excess of a million dollars. The demand for all types of optoelectronic components in communications, computing, automotive, medical and aerospace applications is great, but the high cost of manufacture is constraining growth, so clearly a better method of assembly is needed. In surface mount assembly, advantage is taken of the high surface tension of molten solder to self-align ball grid array packages and flip chip die. However, in these applications, the volume of solder applied as paste by stencil printing is not sufficiently well controlled to achieve the precise alignment required for optoelectronic devices. We believe that the requirement on solder volume control for assembly of optoelectronic devices can be relaxed by designing the bond pads so that the height or alignment of connections is controlled by surface tension of the solder rather than its volume. Our design approach to accomplishing this is to connect auxiliary pads to the primary attachment pad, which act as solder reservoirs. Surface tension causes solder to be redistributed among these pads to achieve a uniform pressure throughout the solder volume. This phenomena is governed by the Young-Laplace equation, ΔP = γκ, in which ΔP represents the difference in pressure within and outside the solder, γ the surface tension of the solder and κ the local curvature of the solder surface. Thus, the design of the set of primary and auxiliary pads is critically important to realizing the desired control of joint height. In this paper we describe the use of the Surface Evolver software package in combination with analytical models, to analyze the behavior of various connection configurations with respect to variations in printed solder volume. Specifically, we calculate the equilibrium shape of the solder surface over the connected set of pads and examine how control of joint height is affected by the number, size and geometry of auxiliary pad configurations. We also discuss results from some preliminary experiments that we are conducting to validate our modeling results.


2016 ◽  
Vol 2016 (1) ◽  
pp. 000711-000720
Author(s):  
Brandon Judd ◽  
Maria Durham

Abstract Voiding under bottom terminated components (BTCs), such as quad-flat no-lead (QFN) components, is a problem which many circuit board assembly houses face on a daily basis. Such components have become very popular in circuit board assembly due to many of their benefits, including their small form factor, excellent thermal and electrical performance, easy PCB trace routing, and reduced lead inductance. Outgassing of flux in the solder paste used to attach QFNs to the PCB during reflow causes voiding under the components, as the gasses cannot escape because there is virtually no standoff under the QFNs. Voiding can have several serious effects on the performance of QFNs including reduced mechanical strength of the solder joint and hot spots under the QFN thermal pad because the voids do not conduct heat well. There are many process methods which are utilized in an attempt to mitigate the voiding issue, such as windowpane stencil designs and reflow profile. In this study, we will evaluate the effect of several other variables on voiding under QFNs, including solder paste powder mesh size, PCB surface metallization, and the reflow environment.


2020 ◽  
Vol 12 ◽  
pp. 184797902094618
Author(s):  
Vincent WC Fung ◽  
Kam Chuen Yung

The process of printed circuit board assembly (PCBA) involves several machines, such as a stencil printer, placement machine and reflow oven, to solder and assemble electronic components onto printed circuit boards (PCBs). In the production flow, some failure prevention mechanisms are deployed to ensure the designated quality of PCBA, including solder paste inspection (SPI), automated optical inspection (AOI) and in-circuit testing (ICT). However, such methods to locate the failures are reactive in nature, which may create waste and require additional effort to be spent re-manufacturing and inspecting the PCBs. Worse still, the process performance of the assembly process cannot be guaranteed at a high level. Therefore, there is a need to improve the performance of the PCBA process. To address the aforementioned challenges in the PCBA process, an intelligent assembly process improvement system (IAPIS) is proposed, which integrates the k-means clustering method and multi-response Taguchi method to formulate a pro-active approach to investigate and manage the process performance. The critical process parameters are first identified by means of k-means clustering and the selected parameters are then used to formulate a set of experimental studies by using the multi-response Taguchi method to optimize the performance of the assembly process. To validate the proposed system, a case study of an electronics manufacturer in the solder paste printing process was conducted. The contributions of this study are two-fold: (i) pressure, blade angle and speed are identified as the critical factors in the solder paste printing process; and (ii) a significant improvement in the yield performance of PCBA can be achieved as a component in the smart manufacturing.


Author(s):  
Changqing Liu ◽  
Paul Conway ◽  
Dezhi Li ◽  
Michael Hendriksen

This research seeks to characterize the micro-mechanical behavior of Sn-Ag-Cu solder bumps/joints generated by fine feature flip chip fabrication and assembly processes. The bumps used for characterization were produced by stencil deposition of solder paste onto an electroless Nickel UBM, followed by a bump-forming reflow soldering process and the final assembly joints were then achieved by a subsequent reflow of die onto a fine feature Printed Circuit Board (PCB). The bumps and joints were aged at either 80°C or 150°C for up to 1.5 months and then analyzed by means of micro-shear testing and nano-indentation techniques. The shear test of the aged bumps showed a slight increase in shear strength after an initial period of aging (∼ 50h) as compared to as-manufactured bumps, but a decrease after longer aging (e.g. 440 h). A brittle Ag3Sn phase formed as large lamellae in the solder and along the interface between the Cu on the PCB during the initial aging, and is attributed to the increase of shear strength, along with the refinement of the bump microstructure. However, as the time of aging extended, the solder bumps were softened due to grain growth and re-crystallization. It was found that the formation of brittle phases in the solder and along the interfaces caused localized stress concentration, which can significantly affect joint reliability. In addition, Nano-testing identified a lamellar Au-rich structure, formed in the solder and interface of the solder/PCB in the joints after the aging process. These are believed to be detrimental to joint reliability.


Author(s):  
Philipp Ritter

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.


Materials ◽  
2021 ◽  
Vol 14 (12) ◽  
pp. 3353
Author(s):  
Marina Makrygianni ◽  
Filimon Zacharatos ◽  
Kostas Andritsos ◽  
Ioannis Theodorakos ◽  
Dimitris Reppas ◽  
...  

Current challenges in printed circuit board (PCB) assembly require high-resolution deposition of ultra-fine pitch components (<0.3 mm and <60 μm respectively), high throughput and compatibility with flexible substrates, which are poorly met by the conventional deposition techniques (e.g., stencil printing). Laser-Induced Forward Transfer (LIFT) constitutes an excellent alternative for assembly of electronic components: it is fully compatible with lead-free soldering materials and offers high-resolution printing of solder paste bumps (<60 μm) and throughput (up to 10,000 pads/s). In this work, the laser-process conditions which allow control over the transfer of solder paste bumps and arrays, with form factors in line with the features of fine pitch PCBs, are investigated. The study of solder paste as a function of donor/receiver gap confirmed that controllable printing of bumps containing many microparticles is feasible for a gap < 100 μm from a donor layer thickness set at 100 and 150 μm. The transfer of solder bumps with resolution < 100 μm and solder micropatterns on different substrates, including PCB and silver pads, have been achieved. Finally, the successful operation of a LED interconnected to a pin connector bonded to a laser-printed solder micro-pattern was demonstrated.


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