A Novel Plating Technique for Realizing Copper Filled TSVs in Silicon Wafers

Through-Silicon-Vias (TSVs) continue to stand out as the most promising technology for electrical interconnections in the microelectronics industry. As package size continues to decrease, TSVs offer an elegant and robust solution for vertical interconnects. They facilitate 3D die stacking while minimizing or even eliminating area consuming planar packaging, allowing for direct signal and power paths through the substrate itself. TSVs can also be fabricated from different materials to desired dimensions to handle the required current level. Plated copper is emerging as the material of choice for TSVs. In this work, electroplated copper TSVs were fabricated successfully and evaluated using cutting and polishing techniques in preparation for image capture. The detailed fabrication process and analysis of the resulting TSVs are presented in this work.

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Through Si Vias Using Liquid Metal Conductors for Re-workable 3D Electronics

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2013dpc-wp13 ◽

2013 ◽

Vol 2013 (DPC) ◽

pp. 001343-001357

Author(s):

George A. Hernandez ◽

Daniel Martinez ◽

Stephen Patenaude ◽

Charles Ellis ◽

Michael Palmer ◽

...

Keyword(s):

Liquid Metal ◽

Failure Analysis ◽

Thermal Stresses ◽

Electrical Contact ◽

Additional Information ◽

Comb Structure ◽

Via Holes ◽

Metal Interconnects ◽

Electroplated Copper ◽

Silicon Vias

This paper describes the design and fabrication of liquid metal interconnects (vias) for 2.5D and 3D integration. The liquid metal is gallium indium eutectic with a melting temperature of approximately 15.7°C that is introduced into via openings of a silicon interposer. This liquid interconnect technology can be integrated with existing interposer technologies, such as capacitors and traditional (solid metal) through-silicon vias (TSVs). In addition, liquid metal interconnects can better accommodate thermal stresses and provide re-workability in case of chip failure. Our research efforts are focused on the integration of multi-chip modules using liquid metal interconnects. Our study encompasses Direct Current (D.C.) measurements and failure analysis using snake and comb structures at low temperature (10 degrees Kelvin) to slightly above room temperature (300 degrees Kelvin). The snake and comb structure allows us to measure electrical shorts and opens, as well as provide estimates of via yield and allows additional information for determination of possible failure mechanisms. In order to make electrical contact to the liquid metal interconnect interposer from both the top and bottom, test coupons have been fabricated with arrays of large numbers of vias. The interposer structure consists of a thin (200 um thick) silicon wafer with via holes filled with liquid metal. The test coupon consists of bottom and top silicon die with a thickness of 500 um. The bottom wafer incorporates a 2 um-thick daisy-chain metallization and 100 um copper tall vias, which are electrically isolated from each other and the underlying Si by patterned AL-X dielectric. The top wafer incorporates an array of 80 um tall, electroplated copper pillars and top daisy-chain metallization. Liquid metal containment mechanisms and structures have also been investigated. In our presentation we will describe the design, fabrication and characterization of this re-workable interposer with liquid metal interconnects. We will present D.C. resistance and X-ray imagery of the liquid metal filled via. In addition, we will provide failure analysis of via yield per chip.

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Underfill Dispensing for 3D Die Stacking with Through Silicon Vias

International Symposium on Microelectronics ◽

10.4071/isom-2012-wa13 ◽

2012 ◽

Vol 2012 (1) ◽

pp. 000548-000553 ◽

Cited By ~ 3

Author(s):

Fuliang Le ◽

S. W. Ricky Lee ◽

Jingshen Wu ◽

Matthew M. F. Yuen

Keyword(s):

Flip Chip ◽

Through Silicon Vias ◽

Flip Chips ◽

Solder Bumps ◽

Die Stacking ◽

Chip Carrier ◽

On Chip ◽

Silicon Vias ◽

3D Package

In this paper, a 3D stacked-die package is developed for the miniaturization and integration of electronic devices. The developed package has a stacked flip-chip-on-chip structure and eight flip chips are arranged in four vertical layers using four silicon chip carriers with through silicon vias (TSVs). In each layer, two flip chips are mounted on the silicon chip carrier with 100 um solder bumps, and multiple TSVs are fabricated in each silicon chip carrier for underfill dispensing purpose. The 3D module with four stacked layers is sequentially assembled by the standard surface mount reflow process and finally mounted to a substrate. In the underfill process, conventional I-pass underfill is used to fill up the gaps of the bottom two layers as it has relatively fast spreading speed. For the top two chip carriers, underfill is dispensed through TSVs to fill the gaps. Unlike the conventional underfill process, the encapsulant in this case would not flow in the gaps by the capillary effect unless the dispensed materials can obtain enough kinetic energy to overcome the surface tension at the end of TSVs, and thus, smooth sidewall, proper dispensing settings and optimized TSV pattern are needed. After underfill, detailed inspections are performed to verify the quality of encapsulation. The results show that the combined I-pass/TSV underfill process gives void-free encapsulation and perfect fillets for the stacked 3D package.

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Reliable Design of Electroplated Copper Through Silicon Vias

Volume 4: Electronics and Photonics ◽

10.1115/imece2010-39283 ◽

2010 ◽

Cited By ~ 12

Author(s):

Xi Liu ◽

Qiao Chen ◽

Venkatesh Sundaram ◽

Sriram Muthukumar ◽

Rao R. Tummala ◽

...

Keyword(s):

System Integration ◽

Coefficient Of Thermal Expansion ◽

Three Dimensional ◽

Interfacial Stress ◽

Through Silicon Vias ◽

Fabrication Defects ◽

Reliable Design ◽

Electroplated Copper ◽

Key Enabling Technologies ◽

Silicon Vias

Through-silicon vias (TSVs), being one of the key enabling technologies for 3D system integration, are being used in various 3D vertically stacked devices. As TSVs are relatively new, there is not enough information in available literature on the thermo-mechanical reliability of TSVs. Due to the high coefficient of thermal expansion (CTE) mismatch between Si and the Cu vias, “Cu pumping” will occur at high temperature and “Cu sinking” will occur at low temperature, which may induce large stress in SiO2, interfacial stress at Cu/SiO2 interface and plastic deformation in Cu core. The thermal-mechanical stress can potentially cause interfacial debonding, cohesive cracking in dielectric layers or Cu core, causing some reliability issues. Thus, in this paper, three-dimensional thermo-mechanical finite-element models have been built to analyze the stress/strain distribution in the TSV structures. A comparative analysis of different via designs, such as circular, square, and annular vias has been performed. In addition, defects due to fabrication such as voids in the Cu core during electroplating and Cu pad undercutting due to over-etching are considered in the models, and it is seen that these fabrication defects are detrimental to TSV reliability.

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Key Enabling Materials for 3DIC Fabrication and Device Performance

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2380-4491-2019-dpc-presentation_tha1_076 ◽

2019 ◽

Vol 2019 (DPC) ◽

pp. 001145-001164

Author(s):

Michael Gallagher ◽

Ed Anzures ◽

Robert Auger ◽

Rosemary Bell ◽

Berry Paul ◽

...

Keyword(s):

Path Length ◽

Adhesive Bonding ◽

Electronics Industry ◽

Device Performance ◽

Critical Part ◽

Bonding Material ◽

Package Size ◽

Die Stacking ◽

Polymer Adhesive ◽

Critical Materials

As the electronics industry reaches the limits of lithographic processing at sub-10nm dimensions, alternate approaches to meet the demand for increasing device density, reducing package size and improving device performance are being explored. Die stacking approaches to reduce the path length between CPU, GPU and memory devices using a heterogeneous 3DIC chip stacking technology have recently been announced, while memory manufacturers have been creating HBM die stacks for use in servers and highspeed applications. At DuPont Electronics & Imaging (E&I), we have been working to enable 3DIC technology through the development of chemicals and processes such as CMP pads and slurries for polishing all the critical materials, chemical cleaners to remove residues, and photoresists to pattern TSVs, pads and pillars. In addition to these materials, E&I also provides permanent materials for hybrid bonding, including electrodeposited copper for TSVs, pads and pillars as well as tin-silver for pillar capping. Another critical part of hybrid bonding is the adhesive bonding material, which needs to be planarized and yet still have sufficient flow to bond at the same time as the Cu-Cu or Cu-SnAg interconnect. This paper will demonstrate how these critical materials can be used together to fabricate 3DIC devices using a conventional bonding tool. Processing of wafers with sub-20 micron pillars has been completed with good metal joining and void-free bonding of the BCB-based polymer adhesive.

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Patterned Permanent Bonding of Benzocyclobutene Based Dielectric Materials for Advanced Wafer Level Packaging

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2014dpc-tp24 ◽

2014 ◽

Vol 2014 (DPC) ◽

pp. 000886-000912

Author(s):

Jong-Uk Kim ◽

Anupam Choubey ◽

Rosemary Bell ◽

Hua Dong ◽

Michael Gallagher ◽

...

Keyword(s):

Wafer Bonding ◽

Dielectric Materials ◽

Wafer Level ◽

Wafer Level Packaging ◽

Integration Schemes ◽

Device Reliability ◽

Package Size ◽

Microelectronics Industry ◽

Improve Device ◽

Joining Process

The microelectronics industry is being continually challenged to decrease package size, lower power consumption and improve device performance for the mobile communication and server markets. In order to keep pace with these requirements, device manufacturers and assembly companies are focused on developing 3D-TSV integration schemes that will require stacking of 50 um thinned wafers with gaps of 15 microns or less. While conventional underfill approaches have been demonstrated for chip to chip and chip to wafer schemes, new materials and processes are required for wafer to wafer bonding given the target bondline and wafer handling issues. Photopatternable, low temperature curable dielectrics offer a potential solution to solve the issues by eliminating the need for flow and material entrapment during the joining process. This should result in a simplified bonding process that enables wafer to wafer bonding with improved device reliability. In this work, we will focus on validating the critical steps including patterning and bonding that are required to demonstrate the utility of this process using an aqueous developable benzocyclobutene based photodielectric material.

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