Underfill Dispensing for 3D Die Stacking with Through Silicon Vias

In this paper, a 3D stacked-die package is developed for the miniaturization and integration of electronic devices. The developed package has a stacked flip-chip-on-chip structure and eight flip chips are arranged in four vertical layers using four silicon chip carriers with through silicon vias (TSVs). In each layer, two flip chips are mounted on the silicon chip carrier with 100 um solder bumps, and multiple TSVs are fabricated in each silicon chip carrier for underfill dispensing purpose. The 3D module with four stacked layers is sequentially assembled by the standard surface mount reflow process and finally mounted to a substrate. In the underfill process, conventional I-pass underfill is used to fill up the gaps of the bottom two layers as it has relatively fast spreading speed. For the top two chip carriers, underfill is dispensed through TSVs to fill the gaps. Unlike the conventional underfill process, the encapsulant in this case would not flow in the gaps by the capillary effect unless the dispensed materials can obtain enough kinetic energy to overcome the surface tension at the end of TSVs, and thus, smooth sidewall, proper dispensing settings and optimized TSV pattern are needed. After underfill, detailed inspections are performed to verify the quality of encapsulation. The results show that the combined I-pass/TSV underfill process gives void-free encapsulation and perfect fillets for the stacked 3D package.

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Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

Volume 5: Electronics and Photonics ◽

10.1115/imece2007-42571 ◽

2007 ◽

Author(s):

Jin Yang ◽

Charles Ume

Keyword(s):

Defect Detection ◽

Flip Chip ◽

Solder Bump ◽

Temporal Coherence ◽

Coherence Analysis ◽

Laser Ultrasound ◽

Surface Mount ◽

Flip Chips ◽

Solder Bumps ◽

Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

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Fundamental Study of the Intermixing of 95Pb-5Sn High-Lead Solder Bumps and 37Pb-63Sn Pre-Solder on Chip-Carrier Substrates

Journal of Electronic Materials ◽

10.1007/s11664-009-0866-4 ◽

2009 ◽

Vol 38 (11) ◽

pp. 2234-2241 ◽

Cited By ~ 6

Author(s):

C. C. Chang ◽

Y. W. Lin ◽

Y. S. Lai ◽

C. R. Kao

Keyword(s):

Fundamental Study ◽

Solder Bumps ◽

Chip Carrier ◽

On Chip ◽

High Lead

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A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias

Proceedings of the 3rd International Workshop on Many-core Embedded Systems - MES '15 ◽

10.1145/2768177.2768178 ◽

2015 ◽

Cited By ~ 1

Author(s):

Mostafa Said ◽

Farhad Mehdipour ◽

Kazuaki Murakami ◽

Mohamed El-Sayed

Keyword(s):

Design Methodology ◽

Network On Chip ◽

Through Silicon Vias ◽

3D Network ◽

On Chip ◽

Silicon Vias

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Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

International Symposium on Microelectronics ◽

10.4071/isom-2012-wp41 ◽

2012 ◽

Vol 2012 (1) ◽

pp. 000891-000905 ◽

Cited By ~ 1

Author(s):

Rainer Dohle ◽

Stefan Härter ◽

Andreas Wirth ◽

Jörg Goßler ◽

Marek Gorywoda ◽

...

Keyword(s):

Flip Chip ◽

Failure Modes ◽

Solder Bump ◽

Void Formation ◽

Lead Free ◽

Large Temperature ◽

Flip Chips ◽

Solder Bumps ◽

Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

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Design and Fabrication of MEMS Based Microphone Module by Using 3D Chip-on-Chip Package

Volume 5: Electronics and Photonics ◽

10.1115/imece2007-42561 ◽

2007 ◽

Author(s):

Jeffery C. C. Lo ◽

S. W. Ricky Lee

Keyword(s):

Flip Chip ◽

Lead Free Solder ◽

Process Flow ◽

Wire Bonds ◽

Solder Bumps ◽

Preliminary Study ◽

Mems Device ◽

Free Solder ◽

On Chip ◽

Electrical Connections

Packaging of the MEMS based microphone is very important as the sensing diaphragm is very fragile. A suitable packaging method is required for the MEMS based microphone. In order to have a better understanding of packaging related issues of microphone, commercially available MEMS based microphone package is studied. Based on the preliminary study, a 3D Chip-on-Chip modulus is selected. The detail process flow of the mentioned package will be discussed in the following sections. Flip chip with lead free solder bumps are used in the proposed 3D Chip-on-Chip modulus. In contrast, wire bonds are used in the commercial MEMS based microphone for electrical connections while die attached is used to provide the mechanical support. The advantages of using flip chip over wire bond in both manufacturability and reliability aspects are discussed. Several MEMS based microphone packaging related issues are studied and evaluated. The detail fabrication and assembly process flow will be presented. A prototype package with MEMS device is fabricated. It can be shown that the proposed 3D Chip-on-Chip modulus is feasible for packaging MEMS based microphone.

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Modelling the Performance of Lead-Free Solder Interconnects for Copper Bumped Flip-Chip Devices

2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2 ◽

10.1115/ipack2003-35356 ◽

2003 ◽

Cited By ~ 2

Author(s):

Hua Lu ◽

Chris Bailey

Keyword(s):

Flip Chip ◽

Printed Circuit Board ◽

Circuit Board ◽

Conductive Adhesives ◽

Solder Interconnects ◽

Flip Chips ◽

Solder Bumps ◽

Solder Volume ◽

Joint Properties ◽

Free Solder

Traditionally, before flip chips can be assembled the dies have to be attached with solder bumps. This process involves the deposition of metal layers on the Al pads on the dies and this is called the under bump metallurgy (UBM). In an alternative process, however, Copper (Cu) columns can be used to replace solder bumps and the UBM process may be omitted altogether. After the bumping process, the bumped dies can be assembled on to the printed circuit board (PCB) by using either solder or conductive adhesives. In this work, the reliability issues of flip chips with Cu column bumped dies have been studied. The flip chip lifetime associated with the solder fatigue failure has been modeled for a range of geometric parameters. The relative importance of these parameters is given and solder volume has been identified as the most important design parameter for long-term reliability. Another important problem that has been studied in this work is the dissolution of protection metals on the pad and Cu column in the reflow process. For small solder joints the amount of Cu which dissolves into the molten solder after the protection layers have worn out may significantly affect solder joint properties.

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Improvement on Fully Filled Through Silicon Vias by Optimized Sputtering and Electroplating Conditions

Materials ◽

10.3390/ma12223713 ◽

2019 ◽

Vol 12 (22) ◽

pp. 3713 ◽

Cited By ~ 1

Author(s):

Fei Zhao

Keyword(s):

Electron Microscope ◽

Integrated Circuit ◽

Seed Layer ◽

High Reliability ◽

Through Silicon Vias ◽

X Ray ◽

Layer Structures ◽

Silicon Vias ◽

Scanning Electron

The high reliability of electroplating through silicon vias (TSVs) is an attractive hotspot in the application of high-density integrated circuit packaging. In this paper, improvements for fully filled TSVs by optimizing sputtering and electroplating conditions were introduced. Particular attention was paid to the samples with different seed layer structures. These samples were fabricated by different sputtering and treatment approaches, and accompanied with various electroplating profile adjustments. The images were observed and characterized by X-ray equipment and a scanning electron microscope (SEM). The results show that optimized sputtering and electroplating conditions can help improve the quality of TSVs, which could be interpreted as the interface effect of the TSV structure.

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Shock and Vibration of Solder Bumped Flip Chip on Organic Coated Copper Boards

Journal of Electronic Packaging ◽

10.1115/1.2792127 ◽

1996 ◽

Vol 118 (2) ◽

pp. 101-104 ◽

Cited By ~ 27

Author(s):

John Lau ◽

Eric Schneider ◽

Tom Baker

Keyword(s):

Mathematical Analysis ◽

Flip Chip ◽

Printed Circuit Board ◽

Circuit Board ◽

Plane Shock ◽

Printed Circuit ◽

Flip Chips ◽

Solder Bumps ◽

Out Of Plane ◽

Vibration Tests

The reliability of solder bumped flip chips on organic coated copper (OCC) printed circuit board (PCB) has been studied by shock and vibration tests and a mathematical analysis. Two different chip sizes (7 mm and 14 mm on a side) have been studied, and the larger chips have many internal solder bumps. For the in-plane and out-of-plane and out-of-plane shock tests, the chips were assembled with and without underfill encapsulants. However, for the out-of-plane vibration tests all the chips were underfilled with epoxy.

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Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

International Symposium on Microelectronics ◽

10.4071/isom-2011-tha3-paper1 ◽

2011 ◽

Vol 2011 (1) ◽

pp. 000953-000960 ◽

Cited By ~ 3

Author(s):

Thomas Oppert ◽

Rainer Dohle ◽

Jörg Franke ◽

Stefan Härter

Keyword(s):

Solder Ball ◽

Flip Chip ◽

Temperature Cycling ◽

Solder Paste ◽

Wafer Level ◽

Solder Alloys ◽

Flip Chips ◽

Fine Pitch ◽

Solder Bumps ◽

Cost Efficient

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

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