Three-Dimensional Stress Singularity Analysis Around the Solder Joints in Electronic Packaging Using Eigen Analysis

2003 ◽  
Author(s):  
Monchai Prukvilailert ◽  
Hideo Koguchi
Keyword(s):  
Mechanical Properties ◽  
Electronic Packaging ◽  
Flip Chip ◽  
Solder Bump ◽  
Three Dimensional ◽  
Stress Singularity ◽  
Dissimilar Materials ◽  
Singularity Analysis ◽  
Contact Angles ◽  
Eigen Analysis

Electronic packaging has several kinds of joint structures of metal, ceramic and polymer. It is well known that the stress singularity occurs at the vertex of joint where the dissimilar materials are bonded together. In this paper, the model in the first analysis is an electronic package using surface mount technology (SMT), the order of stress singularity is investigated, when the mechanical properties of solder, adhesive and resin vary for several values of contact angles between the solder with the chip and with a Cu land. Furthermore, the model in the second analysis is a Flip-Chip-on-Board packaging (FCOB), in which the order of stress singularity at the solder bump is investigated varying the mechanical properties of solder, underfill and the contact angle between the solder bump with a Cu track. After that, the displacement and stress fields for several values of the order of stress singularity are calculated by solving an eigen equation.

Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps

2011 ◽  
Author(s):  
Kohta Nakahira ◽  
Hironori Tago ◽  
Fumiaki Endo ◽  
Ken Suzuki ◽  
Hideo Miura
Keyword(s):  
Mechanical Properties ◽  
Residual Stress ◽  
Thermal Deformation ◽  
Flip Chip ◽  
Flexural Rigidity ◽  
Three Dimensional ◽  
Strain Gauges ◽  
Copper Interconnection ◽  
Induced Stress ◽  
Alignment Structure

Since the thickness of the stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the thermal residual stress distribution appears in the stacked chips due to the periodic alignment of metallic bumps, and they deteriorate the reliability of products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are discussed quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of 4 gauges with different crystallographic directions. This alignment of strain gauges enables to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made by silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper layer was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the rigid joint formation by alloying with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed experimentally that both the hound’s-tooth alignment between a TSV (Through Silicon Via) and a bump and control of mechanical properties of electroplated copper thin films used for the TSV and bump is indispensable in order to minimize the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process induced stress in 3D stacked chips quantitatively.

Finite Element Analysis of Stress Singularities in Attached Flip Chip Packages

2000 ◽  
Vol 122 (4) ◽  
pp. 301-305 ◽  
Author(s):  
A. Q. Xu ◽  
H. F. Nied
Keyword(s):  
Contact Angle ◽  
Finite Element ◽  
Glass Fiber ◽  
Flip Chip ◽  
Three Dimensional ◽  
Stress Singularity ◽  
Local Stress ◽  
Stress Singularities ◽  
Element Analysis ◽  
Three Dimensional Finite Element

Cracking and delamination at the interfaces of different materials in plastic IC packages is a well-known failure mechanism. The investigation of local stress behavior, including characterization of stress singularities, is an important problem in predicting and preventing crack initiation and propagation. In this study, a three-dimensional finite element procedure is used to compute the strength of stress singularities at various three-dimensional corners in a typical Flip-Chip assembled Chip-on-Board (FCOB) package. It is found that the stress singularities at the three-dimensional corners are always more severe than those at the corresponding two-dimensional edges, which suggests that they are more likely to be the potential delamination sites. Furthermore, it is demonstrated that the stress singularity at the upper silicon die/epoxy fillet edge can be completely eliminated by an appropriate choice in geometry. A weak stress singularity at the FR4 board/epoxy edge is shown to exist, with a stronger singularity located at the internal die/epoxy corner. The influence of the epoxy contact angle and the FR4 glass fiber orientation on stress state is also investigated. A general result is that the strength of the stress singularity increases with increased epoxy contact angle. In addition, it is shown that the stress singularity effect can be minimized by choosing an appropriate orientation between the glass fiber in the FR4 board and the silicon die. Based on these results, several guidelines for minimizing edge stresses in IC packages are presented. [S1043-7398(00)00904-X]

Role of Out-of-Plane Coefficient of Thermal Expansion in Electronic Packaging Modeling

1999 ◽  
Vol 122 (2) ◽  
pp. 121-127 ◽  
Author(s):  
Manjula N. Variyam ◽  
Weidong Xie ◽  
Suresh K. Sitaraman
Keyword(s):  
Thermal Expansion ◽  
Electronic Packaging ◽  
Thermal Loading ◽  
Coefficient Of Thermal Expansion ◽  
Plane Deformation ◽  
Three Dimensional ◽  
Dissimilar Materials ◽  
3D Models ◽  
Material Behavior ◽  
Element Analysis

Components in electronic packaging structures are of different dimensions and are made of dissimilar materials that typically have time, temperature, and direction-dependent thermo-mechanical properties. Due to the complexity in geometry, material behavior, and thermal loading patterns, finite-element analysis (FEA) is often used to study the thermo-mechanical behavior of electronic packaging structures. For computational reasons, researchers often use two-dimensional (2D) models instead of three-dimensional (3D) models. Although 2D models are computationally efficient, they could provide misleading results, particularly under thermal loading. The focus of this paper is to compare the results from various 2D, 3D, and generalized plane-deformation strip models and recommend a suitable modeling procedure. Particular emphasis is placed to understand how the third-direction coefficient of thermal expansion (CTE) influences the warpage and the stress results predicted by 2D models under thermal loading. It is seen that the generalized plane-deformation strip models are the best compromise between the 2D and 3D models. Suitable analytical formulations have also been developed to corroborate the findings from the study. [S1043-7398(00)01402-X]

scholarly journals Surface Modification of Additively Manufactured Nitinol by Wet Chemical Etching

Materials ◽  
2021 ◽  
Vol 14 (24) ◽  
pp. 7683
Author(s):  
Denis Nazarov ◽  
Aida Rudakova ◽  
Evgenii Borisov ◽  
Anatoliy Popovich
Keyword(s):  
Mechanical Properties ◽  
Free Surface ◽  
Surface Energy ◽  
Surface Composition ◽  
Three Dimensional ◽  
Physicochemical Characteristics ◽  
Contact Angles ◽  
Free Surface Energy ◽  
Flat Plates ◽  
Water Contact

Three-dimensional printed nitinol (NiTi) alloys have broad prospects for application in medicine due to their unique mechanical properties (shape memory effect and superplasticity) and the possibilities of additive technologies. However, in addition to mechanical properties, specific physicochemical characteristics of the surface are necessary for successful medical applications. In this work, a comparative study of additively manufactured (AM) NiTi samples etched in H2SO4/H2O2, HCl/H2SO4, and NH4OH/H2O2 mixtures was performed. The morphology, topography, wettability, free surface energy, and chemical composition of the surface were studied in detail. It was found that etching in H2SO4/H2O2 practically does not change the surface morphology, while HCl/H2SO4 treatment leads to the formation of a developed morphology and topography. In addition, exposure of nitinol to H2SO4/H2O2 and HCl/H2SO4 contaminated its surface with sulfur and made the surface wettability unstable in air. Etching in NH4OH/H2O2 results in surface cracking and formation of flat plates (10–20 microns) due to the dissolution of titanium, but clearly increases the hydrophilicity of the surface (values of water contact angles are 32–58°). The etch duration (30 min or 120 min) significantly affects the morphology, topography, wettability and free surface energy for the HCl/H2SO4 and NH4OH/H2O2 etched samples, but has almost no effect on surface composition.

Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
Kota Nakahira ◽  
Hironori Tago ◽  
Fumiaki Endo ◽  
Ken Suzuki ◽  
Hideo Miura
Keyword(s):  
Mechanical Properties ◽  
Residual Stress ◽  
Thermal Deformation ◽  
Flip Chip ◽  
Flexural Rigidity ◽  
Three Dimensional ◽  
Strain Gauges ◽  
Copper Interconnection ◽  
Induced Stress ◽  
Alignment Structure

Since the thickness of stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the local distribution of thermal residual stress appears in the stacked chips due to the periodic alignment of metallic bumps, and they sometimes deteriorate mechanical and electrical reliability of electronic products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are investigated quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of four gauges with different crystallographic directions. This alignment of the strain gauges enables us to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made of silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper bump was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the formation of rigid joint by alloying it with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed that not only the control of mechanical properties of electroplated copper thin films, but also the hound’s-tooth alignment of a through silicon via and a bump are indispensable for minimizing the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process-induced stress in 3D stacked chips quantitatively.

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