On-wafer monitoring of charge accumulation and sidewall conductivity in high-aspect-ratio contact holes during SiO[sub 2] etching process

Author(s):  
Butsurin Jinnai ◽  
Toshiyuki Orita ◽  
Mamoru Konishi ◽  
Jun Hashimoto ◽  
Yoshinari Ichihashi ◽  
...  
2013 ◽  
Vol 1553 ◽  
Author(s):  
M. K. Dawood ◽  
Z.H. Mai ◽  
T. H. Ng ◽  
H. Tan ◽  
P.K. Tan ◽  
...  

ABSTRACTSharper nanotips are required for application in nanoprobing systems due to a shrinking contact size with each new transistor technology node. We describe a two-step etching process to fabricate W nanotips with controllable tip dimensions. The first process is an optimized AC electrochemical etching in KOH to fabricate nanotips with a radius of curvature (ROC) down to 90 nm. This was followed by a secondary nanotip sharpening process by laser irradiation in KOH. High aspect ratio nanotips with ROC close to 20 nm were obtained. Finally we demonstrate the application of the fabricated nanotips for nanoprobing on advanced technology SRAM devices.


1986 ◽  
Vol 75 ◽  
Author(s):  
G. V. Treyz ◽  
R. Beach ◽  
R. M. Osgood

AbstractDeep trenches have been etched in crystalline silicon with polarization-controlled, variable-curvature walls. Scan speeds of up to 10mm/s have been demonstrated. A model of the etching process has been developed which is based on a local, melt-enhanced etch rate. Comparisons of model predictions and experimental data are presented.


2016 ◽  
Vol 155 ◽  
pp. 61-66 ◽  
Author(s):  
Peng Sun ◽  
Chengchun Tang ◽  
Xiaoxiang Xia ◽  
Zehan Yao ◽  
Baogang Quan ◽  
...  

Author(s):  
Takahide Murayama ◽  
Toshiyuki Sakuishi ◽  
Yasuhiro Morikawa ◽  
Noriaki Tani ◽  
Kazuya Saitou

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