Direct-Writing of High-Aspect-Ratio Trenches in Silicon

1986 ◽  
Vol 75 ◽  
Author(s):  
G. V. Treyz ◽  
R. Beach ◽  
R. M. Osgood

AbstractDeep trenches have been etched in crystalline silicon with polarization-controlled, variable-curvature walls. Scan speeds of up to 10mm/s have been demonstrated. A model of the etching process has been developed which is based on a local, melt-enhanced etch rate. Comparisons of model predictions and experimental data are presented.

Author(s):  
Tiantong Xu ◽  
Zhi Tao ◽  
Xiao Tan ◽  
Haiwang Li

The manufacture method based on the silicon etching process is one of the most important methods to fabricate micro mechanical structure, e.g. micro-engine. In the processing, the high aspect ratio silicon etch process (HARSE process) is very important to improve the efficiency of structure. At the same time, the surface morphology should be controlled exactly to keep the performance of structure. In this paper, the feasibilities of controlling the surface morphology and Si etch rates were experimentally investigated. In the experiments, the width of structure changes from 15um to 1500um and the depth changes from 50um to 500um. The parameters of surface morphology including sidewall angle, surface roughness, and so on were measured and compared. The influence mechanisms of etching parameters were analyzed. The etching process were completed in a surface technology system (STS) multiplex advanced silicon etcher inductively coupled plasma (ICP) system with SF6/O2 plasma as etching plasma and C4F8 as passivation plasma. In the experiments, the etching experiments were conducted in a low pressure (5–50mTorr), high density, inductively coupled plasma etching reactor (ICP) with a planar coil. The Si etches rates and sidewall angle were investigated as a function of chamber pressure, cathode RF-power, and gas flow. The results indicated that the increasing of total etching time results in an acceleration in etch rate as well as the decrease in sidewall angle (the top width of trench is narrow than the bottom width). Meanwhile, the total passivation time has an opposite effect in the influence of etch rate and sidewall angle. All the experiments indicate that the quick shift between etch and passivation period leads to a smoother surface. An interesting phenomenon were discovered that the etch rate will not change with the changing of width parameter in most of the high aspect ratio silicon etch recipes when the width-depth ratio is upper than 0.34. An experiential function formula were fitted based on four parameters, including width and depth of the structure, and total etching and passivation time.


2010 ◽  
Vol 87 (4) ◽  
pp. 663-667 ◽  
Author(s):  
D. López-Romero ◽  
C.A. Barrios ◽  
M. Holgado ◽  
M.F. Laguna ◽  
R. Casquel

1987 ◽  
Vol 50 (8) ◽  
pp. 475-477 ◽  
Author(s):  
G. V. Treyz ◽  
R. Beach ◽  
R. M. Osgood

2015 ◽  
Vol 40 ◽  
pp. 391-396 ◽  
Author(s):  
Youngseok Lee ◽  
Heeseok Kim ◽  
Shahzada Qamar Hussain ◽  
Sangmyung Han ◽  
Nagarajan Balaji ◽  
...  

2013 ◽  
Vol 1553 ◽  
Author(s):  
M. K. Dawood ◽  
Z.H. Mai ◽  
T. H. Ng ◽  
H. Tan ◽  
P.K. Tan ◽  
...  

ABSTRACTSharper nanotips are required for application in nanoprobing systems due to a shrinking contact size with each new transistor technology node. We describe a two-step etching process to fabricate W nanotips with controllable tip dimensions. The first process is an optimized AC electrochemical etching in KOH to fabricate nanotips with a radius of curvature (ROC) down to 90 nm. This was followed by a secondary nanotip sharpening process by laser irradiation in KOH. High aspect ratio nanotips with ROC close to 20 nm were obtained. Finally we demonstrate the application of the fabricated nanotips for nanoprobing on advanced technology SRAM devices.


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