Feature profile evolution during shallow trench isolation etch in chlorine-based plasmas. I. Feature scale modeling

ABSTRACTMESA is a feature-scale planarization model that predicts the changing topography of the wafer surface during the chemical mechanical polishing (CMP) process used in IC manufacturing. This model has previously been applied to the polish of inter-level dielectrics and copper. The present study is part of a model validation procedure for shallow trench isolation (STI) using experimental feature-scale data. It was carried out using the SpeedFam-IPEC Auriga polisher with SKW Associates 200-mm wafers (SKW3 MIT-STI-mask), Rodel IC 1000/1400 pads and Cabot SS-12 slurry. MESA accounts for observed differences in planarization using Rodel IC1000 with and without foam backing as well as the pattern-density dependence within each die. The data were obtained and plotted in such a way that the active-area and trench-oxide levels are displayed throughout the whole polish, including the points where active area clears to nitride and silicon as well as where trench oxide dishes below the silicon level. The pattern density effect is evident in both cases, but a comparison between the two pads shows less pattern density effect and improved planarization with the single IC 1000 pad.MESA is shown to predict the details of the topographical evolution for STI CMP on the feature scale. When validated by fitting the pad constants k1 and k2 to describe the planarization, MESA provides reasonably accurate predictions for the polish of any oxide pattern structure as long as the same CMP process is used.

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Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

10.31399/asm.cp.istfa1998p0011 ◽

1998 ◽

Author(s):

I. De Wolf ◽

G. Groeseneken ◽

H.E. Maes ◽

M. Bolt ◽

K. Barla ◽

...

Keyword(s):

Raman Spectroscopy ◽

Mechanical Stress ◽

Defect Formation ◽

Active Area ◽

Wet Oxidation ◽

Leakage Currents ◽

Shallow Trench Isolation ◽

Micro Raman Spectroscopy ◽

Silicon Devices ◽

Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

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Fabricating high performance n-channel lateral double diffused metal–oxide–semiconductor transistors utilizing the shallow trench isolation as a salicide blocking mask of the drift region

Current Applied Physics ◽

10.1016/j.cap.2007.10.086 ◽

2009 ◽

Vol 9 (1) ◽

pp. 9-12 ◽

Cited By ~ 3

Author(s):

Kee-Yeol Na ◽

Yeong-Seuk Kim

Keyword(s):

Metal Oxide ◽

High Performance ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Drift Region ◽

Shallow Trench Isolation ◽

Trench Isolation

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Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽

10.1557/mrs2002.244 ◽

2002 ◽

Vol 27 (10) ◽

pp. 743-751 ◽

Cited By ~ 77

Author(s):

Rajiv K. Singh ◽

Rajeev Bajaj

Keyword(s):

Surface Topography ◽

Process Integration ◽

Semiconductor Industry ◽

Chemical Mechanical Planarization ◽

Shallow Trench Isolation ◽

Trench Isolation ◽

Fundamental Understanding ◽

Copper Polishing ◽

Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

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