Nonlinear integrated quantum electro-optic circuits

Future quantum computation and networks require scalable monolithic circuits, which incorporate various advanced functionalities on a single physical substrate. Although substantial progress for various applications has already been demonstrated on different platforms, the range of diversified manipulation of photonic states on demand on a single chip has remained limited, especially dynamic time management. Here, we demonstrate an electro-optic device, including photon pair generation, propagation, electro-optical path routing, as well as a voltage-controllable time delay of up to ~12 ps on a single Ti:LiNbO3waveguide chip. As an example, we demonstrate Hong-Ou-Mandel interference with a visibility of more than 93 ± 1.8%. Our chip not only enables the deliberate manipulation of photonic states by rotating the polarization but also provides precise time control. Our experiment reveals that we have full flexible control over single-qubit operations by harnessing the complete potential of fast on-chip electro-optic modulation.

Download Full-text

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽

10.3390/mi12020183 ◽

2021 ◽

Vol 12 (2) ◽

pp. 183

Author(s):

Jose Ricardo Gomez-Rodriguez ◽

Remberto Sandoval-Arechiga ◽

Salvador Ibarra-Delgado ◽

Viktor Ivan Rodriguez-Abdala ◽

Jose Luis Vazquez-Avila ◽

...

Keyword(s):

Single Chip ◽

Synthesis Time ◽

Networks On Chip ◽

Data Dependencies ◽

Layered Architecture ◽

Systems On Chip ◽

Challenges And Opportunities ◽

Computing Platforms ◽

On Chip ◽

Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

Download Full-text

Elementary General Music Performances and Teachers’ Perceptions of Stress

Update Applications of Research in Music Education ◽

10.1177/87551233211010401 ◽

2021 ◽

pp. 875512332110104

Author(s):

Jennifer Potter

Keyword(s):

Time Management ◽

Music Teachers ◽

Management Control ◽

Elementary Music ◽

General Music ◽

Teachers Perceptions ◽

Time Control ◽

Elementary General Music ◽

And Performance ◽

The Impact

The purpose of investigation was to examine the perceptions of elementary music teachers concerning the preparation of elementary music performances and the impact on their perceived stress. Participants were practicing elementary general music teachers ( N = 3) representing three different elementary schools from a metropolitan area in the Midwest. All participants were interviewed twice over a period of two months via Zoom. Data were analyzed through an open coding process (Gibbs, 2007), which yielded three themes: time management, control, and isolation. Facets of time management included strategic planning, organizational techniques, and instructional time; control concerned scheduling, repertoire selection, equipment, and performance venues; and isolation pertained to relationships with colleagues and administrators and an overwhelming amount of responsibility. These findings indicate the importance of acknowledging various stressors affecting music educators and how those might positively and negatively affect teachers and students.

Download Full-text

On-Chip Dual-Band Rectangular Slot Antenna for Single-Chip Millimeter-Wave Identification Tag in Standard CMOS Technology

IEEE Transactions on Antennas and Propagation ◽

10.1109/tap.2017.2710215 ◽

2017 ◽

Vol 65 (8) ◽

pp. 3858-3868 ◽

Cited By ~ 8

Author(s):

Pascal Burasa ◽

Tarek Djerafi ◽

Nicolas G. Constantin ◽

Ke Wu

Keyword(s):

Millimeter Wave ◽

Cmos Technology ◽

Dual Band ◽

Slot Antenna ◽

Single Chip ◽

Rectangular Slot ◽

On Chip ◽

Wave Identification

Download Full-text

Erratum: On-chip microwave-to-optical quantum coherent converter based on a superconducting resonator coupled to an electro-optic microresonator [Phys. Rev. A 94 , 053815 (2016)]

Physical Review A ◽

10.1103/physreva.98.069902 ◽

2018 ◽

Vol 98 (6) ◽

Author(s):

C. Javerzac-Galy ◽

K. Plekhanov ◽

N. R. Bernier ◽

L. D. Toth ◽

A. K. Feofanov ◽

...

Keyword(s):

Superconducting Resonator ◽

Electro Optic ◽

On Chip

Download Full-text

An overview of on-chip buses

Facta universitatis - series Electronics and Energetics ◽

10.2298/fuee0603405m ◽

2006 ◽

Vol 19 (3) ◽

pp. 405-428 ◽

Cited By ~ 10

Author(s):

Milica Mitic ◽

Mile Stojcev

Keyword(s):

Interconnection Networks ◽

Electronics Industry ◽

Design Reuse ◽

Design Teams ◽

Single Chip ◽

Data Transfers ◽

System On A Chip ◽

Design Interfaces ◽

On Chip ◽

Levels Of Integration

The electronics industry has entered the era of multi-million-gate chips, and there Xs no turning back. This technology promises new levels of integration on a single chip, called the System-on-a-Chip (SoC) design, but also presents significant challenges to the chip designer. Processing cores on a single chip, may number well into the high tens within the next decade, given the current rate of advancements, [1]. Interconnection networks in such an environment are, therefore, becoming more and more important [2]. Currently on-chip interconnection networks are mostly implemented using buses. For SoC applications, design reuse becomes easier if standard internal connection buses are used for interconnecting components of the design. Design teams developing modules intended for future reuse can design interfaces for the standard bus around their particular modules. This allows future designers to slot the reuse module into their new design simply, which is also based around the same standard bus [3]. In this paper we give an overview of the more popular on-chip bus-based interconnection networks such as AMBA, Avalon CoreConnect, STBus, Wishbone, etc. The main characteristics of the considered buses in respect to topology, arbitration method, bus-width, and types of data transfers are discussed.

Download Full-text

Critical Issues of TSV and 3D IC Integration

Journal of Microelectronics and Electronic Packaging ◽

10.4071/1551-4897-7.1.35 ◽

2010 ◽

Vol 7 (1) ◽

pp. 35-43 ◽

Cited By ~ 9

Author(s):

John H. Lau

Keyword(s):

System On Chip ◽

The Other ◽

Single Chip ◽

3D Ic ◽

Moore’S Law ◽

Moore's Law ◽

Other Hand ◽

Critical Issues ◽

Research Problems ◽

On Chip

Moore's law has been the most powerful driver for the development of the microelectronic industry. This law is grounded in lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration. However, there are many critical issues for 3D IC integration. In this study, some of the critical issues will be discussed and some potential solutions or research problems will be proposed.

Download Full-text

Deploying Hard Real-Time Control Software on Chip-Multiprocessors

2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications ◽

10.1109/rtcsa.2010.43 ◽

2010 ◽

Cited By ~ 2

Author(s):

Dai N. Bui ◽

Hiren D. Patel ◽

Edward A. Lee

Keyword(s):

Real Time ◽

Chip Multiprocessors ◽

Real Time Control ◽

Control Software ◽

Time Control ◽

On Chip ◽

Hard Real Time

Download Full-text

On-chip boost regulator with projected off- and on-time control

Journal of Zhejiang University SCIENCE A ◽

10.1631/jzus.a0920160 ◽

2009 ◽

Vol 10 (8) ◽

pp. 1223-1230 ◽

Cited By ~ 6

Author(s):

Xiao-ru Xu ◽

Meng-lian Zhao ◽

Xiao-bo Wu

Keyword(s):

Time Control ◽

Boost Regulator ◽

On Chip

Download Full-text

Integrated Photonic Circuits in Gallium Nitride and Aluminum Nitride

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156414500013 ◽

2014 ◽

Vol 23 (01n02) ◽

pp. 1450001 ◽

Cited By ~ 3

Author(s):

Chi Xiong ◽

Wolfram Pernice ◽

Carsten Schuck ◽

Hong X. Tang

Keyword(s):

High Speed ◽

Optical Signal ◽

Silicon Substrates ◽

Material System ◽

Group Iii ◽

Electro Optic ◽

New Material ◽

Nanophotonic Circuits ◽

Group Iii Nitride ◽

On Chip

Integrated optics is a promising optical platform both for its enabling role in optical interconnects and applications in on-chip optical signal processing. In this paper, we discuss the use of group III-nitride (GaN, AlN) as a new material system for integrated photonics compatible with silicon substrates. Exploiting their inherent second-order nonlinearity we demonstrate and second, third harmonic generation in GaN nanophotonic circuits and high-speed electro-optic modulation in AlN nanophotonic circuits.

Download Full-text