scholarly journals Cointegration of single-transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware

2021 ◽  
Vol 7 (32) ◽  
pp. eabg8836
Author(s):  
Joon-Kyu Han ◽  
Jungyeop Oh ◽  
Gyeong-Jun Yun ◽  
Dongeun Yoo ◽  
Myung-Su Kim ◽  
...  

Cointegration of multistate single-transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide semiconductor (CMOS) fabrication. The neurons and synapses were integrated on the same plane with the same process because they have the same structure of a metal-oxide semiconductor field-effect transistor with different functions such as homotype. By virtue of 100% CMOS compatibility, it was also realized to cointegrate the neurons and synapses with additional CMOS circuits. Such cointegration can enhance packing density, reduce chip cost, and simplify fabrication procedures. The multistate single-transistor neuron that can control neuronal inhibition and the firing threshold voltage was achieved for an energy-efficient and reliable neural network. Spatiotemporal neuronal functionalities are demonstrated with fabricated single-transistor neurons and synapses. Image processing for letter pattern recognition and face image recognition is performed using experimental-based neuromorphic simulation.

2021 ◽  
Author(s):  
Kamal Y. Kamal ◽  
Radu Muresan ◽  
Arafat Al-Dweik

<p>This article reviews complementary metal-oxide-semiconductor (CMOS) based physically unclonable functions (PUFs) in terms of types, structures, metrics, and challenges. The article reviews and classifies the most basic PUF types. The article reviews the basic variations originated during a metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process. Random <a>variations</a> at transistor level lead to acquiring unique properties for electronic chips. These variations help a PUF system to generate a unique response. This article discusses various concepts which allow for more variations at CMOS technology, layout, masking, and design levels. It also discusses various PUF related topics.</p>


1998 ◽  
Vol 37 (Part 1, No. 11) ◽  
pp. 5926-5931
Author(s):  
Masahiro Shimizu ◽  
Takashi Kuroi ◽  
Masahide Inuishi ◽  
Hideaki Arima ◽  
Haruhiko Abe ◽  
...  

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