System-on-Chip Integration

2002 ◽  
Vol 12 (02) ◽  
pp. 325-332
Author(s):  
ROBERT R. DOERING
Keyword(s):  
Low Cost ◽  
System On Chip ◽  
Foreseeable Future ◽  
Digital Cmos ◽  
Chip Area ◽  
Traditional System ◽  
Time Performance ◽  
Wide Range ◽  
On Chip ◽  
Process Complexity

Numerous "signal-processing products" are now driving the semiconductor market for SOC solutions enabling real-time performance, low-cost, low-power, portability, etc. A primary limit on the types of electronic (or other) functions that will be integrated into future SOCs is cost of integration, which tends to grow non-linearly with process complexity and chip area. A near-continuum of System-on/in-X solutions is emerging between traditional System-on-Chip and System-on-Board. These approaches span the tradeoff between bandwidth and cost. For the foreseeable future, digital CMOS will continue to serve as a "host platform" for integrating a wide range of mechanical, optical, biological, and, perhaps, even "quantum" technologies.

scholarly journals An Efficient Cache Organization for On-Chip Multiprocessor Networks

2015 ◽  
Vol 5 (3) ◽  
pp. 503
Author(s):  
Medhat Awadalla ◽  
Ahmed M. Sadek
Keyword(s):  
High Performance ◽  
Cache Coherence ◽  
Low Cost ◽  
System On Chip ◽  
Cache Memory ◽  
Processing Unit ◽  
Single Chip ◽  
Chip Area ◽  
Shared Cache ◽  
On Chip

To meet the growing computation-intensive applications and the needs of low-power, high-performance systems, the number of computing resources in single-chip has enormously increased. By adding many computing resources to build a system in System-on-Chip, its interconnection between each other becomes another challenging issue. In most System-on-Chip applications, a shared bus interconnection which needs an arbitration logic to serialize several bus access requests, is adopted to communicate with each integrated processing unit because of its low-cost and simple control characteristics. This paper focuses on the interconnection design issues of area, power and performance of chip multi-processors with shared cache memory. It shows that having shared cache memory contributes to the performance improvement, however, typical interconnection between cores and the shared cache using crossbar occupies most of the chip area, consumes a lot of power and does not scale efficiently with increased number of cores. New interconnection mechanisms are needed to address these issues. This paper proposes an architectural paradigm in an attempt to gain the advantages of having shared cache with the avoidance of penalty imposed by the crossbar interconnect. The proposed architecture achieves smaller area occupation allowing more space to add additional cache memory. It also reduces power consumption compared to the existing crossbar architecture. Furthermore, the paper presents a modified cache coherence algorithm called Tuned-MESI. It is based on the typical MESI cache coherence algorithm however it is tuned and tailored for the suggested architecture. The achieved results of the conducted simulated experiments show that the developed architecture produces less broadcast operations compared to the typical algorithm.

A low-cost, wide-band DCO with an on-chip 3-D solenoid inductor in 0.13 μm digital CMOS

2013 ◽  
Vol 74 (3) ◽  
pp. 507-515
Author(s):  
HyungGu Park ◽  
SoYoung Kim ◽  
Kang-Yoon Lee
Keyword(s):  
Low Cost ◽  
Wide Band ◽  
Digital Cmos ◽  
On Chip

First Intel Low-Cost IA Atom-based System-On-Chip for Nettop/Netbook

2009 ◽  
Author(s):  
Suphachai Sutanthavibul ◽  
Suresh Kumar Perabala
Keyword(s):  
Low Cost ◽  
System On Chip ◽  
On Chip

scholarly journals Low Complexity System on Chip Design to Acquire Signals from MOS Gas Sensor Applications

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6552
Author(s):  
Juan B. Talens ◽  
Jose Pelegri-Sebastia ◽  
Maria Jose Canet
Keyword(s):  
Gas Sensor ◽  
Low Voltage ◽  
Low Cost ◽  
Low Complexity ◽  
System On Chip ◽  
Working Environment ◽  
Sigma Delta ◽  
Sensor Applications ◽  
Analog Signals ◽  
On Chip

Analog signals from gas sensors are used to recognize all types of VOC (Volatile Organic Compound) substances, such as toxic gases, tobacco or ethanol. The processes to recognize these substances include acquisition, treatment and machine learning for classification, which can all be efficiently implemented on a Field Programmable Gate Array (FPGA) aided by Low-Voltage Differential Signaling (LVDS). This article proposes a low-cost 11-bit effective number of bits (ENOB) sigma-delta Analog to Digital Converter (ADC), with an SNR of 75.97 dB and an SFDR of 72.28 dB, whose output is presented on screen in real time, thanks to the use of a Linux System on Chip (SoC) system that enables parallelism, high-level programming and provides a working environment for the scientific treatment of gas sensor signals. The high frequency achieved by the implemented ADC allows for multiplexing the capture of several analog signals with an optimal resolution. Additionally, several ADCs can be implemented in the same FPGA so several analog signals can be digitalized in parallel.

scholarly journals Surface-enhanced mid-infrared absorption spectroscopy using miniaturized-disc metasurface

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Mitchell Semple ◽  
Ashwin K. Iyer
Keyword(s):  
Infrared Spectroscopy ◽  
Signal To Noise Ratio ◽  
Low Cost ◽  
Unit Cell ◽  
Mid Infrared ◽  
Wide Range ◽  
Surface Enhanced ◽  
Identification Measurements ◽  
Vibrational Bands ◽  
On Chip

AbstractSurface-enhanced infrared spectroscopy is an important technique for improving the signal-to-noise ratio of spectroscopic material identification measurements in the mid-infrared fingerprinting region. However, the lower bound of the fingerprinting region receives much less attention due to a scarcity of transparent materials, more expensive sources, and weaker plasmonic effects. In this paper, we present a miniaturized metasurface unit cell for surface-enhanced infrared spectroscopy of the 15-$$\upmu$$ μ m vibrational band of CO$$_{2}$$ 2 . The unit cell consists of a gold disc, patterned along the edge with fine gaps/wires to create a resonant metamaterial liner. In simulation, our plasmonic metamaterial-lined disc achieves greater than $$4\times$$ 4 × the average field intensity enhancement of a comparable dipole array and a miniaturized size of $$\lambda _0/5$$ λ 0 / 5 using complex, 100-nm features that are patterned using 100-kV electron-beam lithography. In a simple experiment, the metamaterial-lined disc metasurface shows a high tolerance to fabrication imperfections and enhances the absorption of CO$$_{2}$$ 2 at 15 $$\upmu$$ μ m. The resonant wavelength and reflection magnitude can be tuned over a wide range by adjusting the liner feature sizes and the metasurface array pitch to target other vibrational bands. This work is a step toward low-cost, more compact on-chip integrated gas sensors.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

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