A Novel One SWS-FET Transistor for AND/OR Logic Gate

2018 ◽  
Vol 27 (03n04) ◽  
pp. 1840019
Author(s):  
Bander Saman ◽  
E. Heller ◽  
F. C. Jain
Keyword(s):  
Quantum Well ◽  
Logic Gate ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Behavioral Model ◽  
Charge Carrier Concentration ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
Effect Transistor ◽  
Or Logic Gate

This paper presents the design and modeling of AND/OR logic gate using one high-mobility n-channel spatial wave-function switched field-effect transistor (n-SWS-FET), which provide a significant reduction of cell area and power dissipation. In SWSFET, the channel between source and drain has two or more quantum well (QW) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum well layers and it causes the switching of charge carriers from one channel to other channel of the SWS device. This switching property promises to build AND/OR logic gate with one n-SWS-FET transistor, where Complementary Metal Oxide Semiconductor (CMOS) AND/OR gate is built by 6 transistors. The proposed gate configures as AND/OR by change sources signal. The SWS-FET device with two well Si/Si0.5Ge0.5 has been modeled using Berkeley Short-channel IGFET Model (BSIM4.6.0) and Analog Behavioral Model (ABM), the model is suitable for transient analysis at circuit level. This model is optimized for AND/OR logic and used to replace a conventional CMOS logic.

Logic Gates Design and Simulation Using Spatial Wavefunction Switched (SWS) FETs

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550008 ◽  
Author(s):  
Bander Saman ◽  
P. Mirdha ◽  
M. Lingalugari ◽  
P. Gogna ◽  
F. C. Jain ◽  
...  
Keyword(s):  
Quantum Wells ◽  
Field Effect Transistors ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Behavioral Model ◽  
Charge Carrier Concentration ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
Proposed Model ◽  
High Band

This paper presents the design and modeling of logic gates using two channel spatial wavefunction switched field-effect transistors (SWSFETs) it is also known as a twin-drain MOSFET. In SWSFETs, the channel between source and drain has two or more quantum wells (QWs) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum wells layers and it causes the switching of charge carriers from one channel to other channel of the device. The first part of this paper shows the characteristics of n-channel SWSFET model, the second part provides the circuit topology for the SWSFET inverter and universal gates- NAND, AND, NOR,OR, XOR and XOR. The proposed model is based on integration between Berkeley Short-channel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level. The results show that all basic two-input logic gates can be implanted by using n-channel SWSFET only, It covers less area compared with CMOS (Complementary metal–oxide–semiconductor) gates. The NAND-NOR can be performed by three SWSFET, moreover the exclusive-NOR “XNOR” can be done by four SWSFET transistors also AND, OR, XOR gates require two additional SWSFET for inverting.

Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation

2017 ◽  
Vol 26 (03) ◽  
pp. 1740009 ◽  
Author(s):  
Bander Saman ◽  
P. Gogna ◽  
El-Sayed Hasaneen ◽  
J. Chandy ◽  
E. Heller ◽  
...  
Keyword(s):  
Quantum Well ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Random Access ◽  
Behavioral Model ◽  
Charge Carrier Concentration ◽  
Oxide Semiconductor ◽  
Effect Transistor ◽  
The Stability ◽  
Transistor Mos

This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWSFET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Performance Evaluation of Silicon-Transition Metal Dichalcogenides Heterostructure Based Steep Subthreshold Slope-Field Effect Transistor Using Non-Equilibrium Green’s Function

2020 ◽  
Vol 18 (6) ◽  
pp. 468-476
Author(s):  
Prateek Kumar ◽  
Maneesha Gupta ◽  
Naveen Kumar ◽  
Marlon D. Cruz ◽  
Hemant Singh ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Molybdenum Disulphide ◽  
Short Channel ◽  
Tungsten Disulphide ◽  
Channel Effects ◽  
Effect Transistor

With technology invading nanometer regime performance of the Metal-Oxide-semiconductor Field Effect Transistor is largely hampered by short channel effects. Most of the simulation tools available do not include short channel effects and quantum effects in the analysis which raises doubt on their authenticity. Although researchers have tried to provide an alternative in the form of tunnel field-effect transistors, junction-less transistors, etc. but they all suffer from their own set of problems. Therefore, Metal-Oxide-Semiconductor Field-Effect Transistor remains the backbone of the VLSI industry. This work is dedicated to the design and study of the novel tub-type Metal-Oxide-Semiconductor Field-Effect Transistor. For simulation Non-Equilibrium Green’s Function is used as the primary model of simulation. The device is analyzed under different physical variations like work function, permittivity, and interface trap charge. This work uses Silicon-Molybdenum Disulphide heterojunction and Silicon-Tungsten Disulphide heterojunction as channel material. Results for both the heterojunctions are compared. It was analyzed that Silicon-Molybdenum Disulphide heterojunction provides better linearity and Silicon-Tungsten Disulphide heterojunction provides better switching speed than conventional Metal-Oxide-Semiconductor Field-Effect Transistor.

scholarly journals Fault Modeling of Graphene Nanoribbon FET Logic Circuits

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 851 ◽  
Author(s):  
Gil-Tomàs ◽  
Gracia-Morán ◽  
Saiz-Adalid ◽  
Gil-Vicente
Keyword(s):  
Field Effect Transistor ◽  
Fault Tolerant ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Graphene Nanoribbon ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Fault Models ◽  
New Materials ◽  
Effect Transistor

Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

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