EFFECTS OF PARAMETER VARIATIONS ON TIMING CHARACTERISTICS OF CLOCKED REGISTERS

2009 ◽  
Vol 18 (07) ◽  
pp. 1309-1320
Author(s):  
WILLIAM R. ROBERTS ◽  
DIMITRIOS VELENIS
Keyword(s):  
Supply Voltage ◽  
Setup Time ◽  
Oxide Thickness ◽  
Propagation Delay ◽  
Timing Constraints ◽  
Power Supply Voltage ◽  
Synchronous System ◽  
Data Propagation ◽  
Gate Oxide Thickness ◽  
Parameter Variations

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay to variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different register designs. Furthermore, design modifications are proposed that enhance the robustness of each register to variation effects.

Strained Silicon Devices

2009 ◽  
Vol 156-158 ◽  
pp. 61-68 ◽  
Author(s):  
Manfred Reiche ◽  
O. Moutanabbir ◽  
Jan Hoentschel ◽  
U.M. Gösele ◽  
Stefan Flachowsky ◽  
...  
Keyword(s):  
Physical Mechanism ◽  
Supply Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Current Drive ◽  
Strained Silicon ◽  
Silicon Devices ◽  
Gate Oxide Thickness ◽  
Carrier Velocity

Strained silicon channels are one of the most important Technology Boosters for further Si CMOS developments. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels, resulting in higher current drive under a fixed supply voltage and gate oxide thickness. The physical mechanism of mobility enhancement, methods of strain generation and their application for advanced VLSI devices is reviewed.

scholarly journals Analytical 2D Modeling of Surface Potential and Threshold Voltage for Lightly Doped Substrate NMOS

2019 ◽  
Vol 8 (4) ◽  
pp. 12108-12111
Keyword(s):  
Threshold Voltage ◽  
Analytical Modeling ◽  
Field Effect Transistor ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Problems ◽  
Gate Oxide Thickness ◽  
Effect Transistor

Reducing the device dimensions leads to scaling of various parameters like junction depth, supply voltage and gate oxide thickness and results to the variation of threshold voltage. Threshold voltage variations can cause serious design problems. So threshold voltage can be adjusted by various ways which is the most important parameter of the MOSFET. This paper depicts the analytical modeling and simulation of Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The expression for potential at source and drain ends and threshold voltage has been derived and the theoretical values are compared with simulated values. From simulation results from SILVACO TAD tool, threshold voltage of 0.22V is achieved at a work-function of 4.12eV

Effects of Inversion Layer Quantization and Polysilicon Gate Depletion on Tunneling Current of Ultra-Thin SiO2 Gate Material

1999 ◽  
Vol 567 ◽  
Author(s):  
S. Saha ◽  
G. Srinivasan ◽  
G. A. Rezvani ◽  
M. Farr
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Inversion Layer ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
The Impact

ABSTRACTWe have investigated the impact of inversion layer quantization and polysilicon-gate depletion effects on the direct-tunneling gate-leakage current and reliability of ultra-thin silicon-dioxide gate dielectric. The gate-leakage current was measured for nMOSFET devices with gate oxide thickness down to 3 nm. A simulation-based methodology was used to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with and without the quantum mechanical and polysilicon depletion effects. The simulation results indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. Our data, also, show that in order to maintain a leakage current ≥ 1 A/cm2 for 1 V operation, the effective gate oxide thickness must be ≥ 2.2 nm.

Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout

2011 ◽  
Vol E94-C (6) ◽  
pp. 1072-1075
Author(s):  
Tadashi YASUFUKU ◽  
Yasumi NAKAMURA ◽  
Zhe PIAO ◽  
Makoto TAKAMIYA ◽  
Takayasu SAKURAI
Keyword(s):  
Power Supply ◽  
Voltage Dependence ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Place And Route ◽  
Delay Variation

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing

2016 ◽  
Vol E99.C (10) ◽  
pp. 1219-1225
Author(s):  
Masahiro ISHIDA ◽  
Toru NAKURA ◽  
Takashi KUSAKA ◽  
Satoshi KOMATSU ◽  
Kunihiro ASADA
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Voltage Control ◽  
Fault Testing ◽  
Power Supply Voltage ◽  
Delay Fault ◽  
Delay Fault Testing

AlInAs/GaInAs on InP HEMTs for low power supply voltage operation of high power-added efficiency microwave amplifiers

1993 ◽  
Vol 29 (15) ◽  
pp. 1324 ◽  
Author(s):  
L.E. Larson ◽  
M.M. Matloubian ◽  
J.J. Brown ◽  
A.S. Brown ◽  
M. Thompson ◽  
...  
Keyword(s):  
Low Power ◽  
High Power ◽  
Power Supply ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Power Added Efficiency ◽  
Microwave Amplifiers

Design of the variable frequency oscillator in DC-DC converter

Circuit World ◽  
2019 ◽  
Vol 45 (2) ◽  
pp. 80-85
Author(s):  
Tian Lei ◽  
Nan Gong ◽  
Li Wang ◽  
Qin Qin Li ◽  
Heng Wei Wang
Keyword(s):  
Supply Voltage ◽  
Operating Frequency ◽  
Maximum Deviation ◽  
Variable Frequency ◽  
Cmos Process ◽  
Power Supply Voltage ◽  
Output Stage ◽  
Content Type ◽  
Oscillator Frequency ◽  
Light Load

Purpose Because of the logic delay in the converter, the minimum turn on time of the switch is influenced by the constant time. When the inductor current gets to the threshold of the chip, the control signal will delay for a period. This makes the inductor current rising with the increasing of the clock and leads to the load current out of control. Thus, this paper aims to design an oscillator with a variable frequency protection function. Design/methodology/approach This paper presents an oscillator with the reducing frequency applied in the DC-DC converter. When the converter works normally, the operating frequency of the oscillator is 1.5 MHz. So the inductor current has enough time to decay and prevent the power transistor damaging. After the abnormal condition, the converter returns to the normal operating mode automatically. Findings Based on 0.5 µm CMOS process, simulated by the HSPICE, the simulation results shows that the frequency of the oscillator linearly decreases from 1.5 MHz to 380 KHz when the feedback voltage less than 0.2 V. The maximum deviation of the oscillator frequency is only 6 per cent from −50°C to 125°C within the power supply voltage of 2.7-5.5 V. Originality/value When the light load occurs at the output stage, the oscillator frequency will decrease as the load voltage drops. The test results shows that when the circuit works in the normal condition, the oscillator frequency is 1.5 MHz. When the load decreased, the operating frequency is dropped dramatically.

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