Design of the variable frequency oscillator in DC-DC converter

Circuit World ◽  
2019 ◽  
Vol 45 (2) ◽  
pp. 80-85
Author(s):  
Tian Lei ◽  
Nan Gong ◽  
Li Wang ◽  
Qin Qin Li ◽  
Heng Wei Wang
Keyword(s):  
Supply Voltage ◽  
Operating Frequency ◽  
Maximum Deviation ◽  
Variable Frequency ◽  
Cmos Process ◽  
Power Supply Voltage ◽  
Output Stage ◽  
Content Type ◽  
Oscillator Frequency ◽  
Light Load

Purpose Because of the logic delay in the converter, the minimum turn on time of the switch is influenced by the constant time. When the inductor current gets to the threshold of the chip, the control signal will delay for a period. This makes the inductor current rising with the increasing of the clock and leads to the load current out of control. Thus, this paper aims to design an oscillator with a variable frequency protection function. Design/methodology/approach This paper presents an oscillator with the reducing frequency applied in the DC-DC converter. When the converter works normally, the operating frequency of the oscillator is 1.5 MHz. So the inductor current has enough time to decay and prevent the power transistor damaging. After the abnormal condition, the converter returns to the normal operating mode automatically. Findings Based on 0.5 µm CMOS process, simulated by the HSPICE, the simulation results shows that the frequency of the oscillator linearly decreases from 1.5 MHz to 380 KHz when the feedback voltage less than 0.2 V. The maximum deviation of the oscillator frequency is only 6 per cent from −50°C to 125°C within the power supply voltage of 2.7-5.5 V. Originality/value When the light load occurs at the output stage, the oscillator frequency will decrease as the load voltage drops. The test results shows that when the circuit works in the normal condition, the oscillator frequency is 1.5 MHz. When the load decreased, the operating frequency is dropped dramatically.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

A High-Order CMOS Bandgap Voltage Reference

2014 ◽  
Vol 989-994 ◽  
pp. 1165-1168
Author(s):  
Qian Neng Zhou ◽  
Yun Song Li ◽  
Jin Zhao Lin ◽  
Hong Juan Li ◽  
Chen Li ◽  
...  
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
High Order ◽  
Cmos Process ◽  
Voltage Reference ◽  
Power Supply Voltage ◽  
Power Supply Rejection Ratio ◽  
Voltage Deviation ◽  
Bandgap Voltage Reference

A high-order bandgap voltage reference (BGR) is designed by adopting a current which is proportional to absolute temperature T1.5. The high-order BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the designed high-order BGR achieves temperature coefficient of 2.54ppm/°C when temperature ranging from-55°C to 125°C. The high-order BGR at 10Hz, 100Hz, 1kHz, 10kHz and 100kHz achieves, respectively, the power supply rejection ratio of-64.01dB, -64.01dB, -64dB, -63.5dB and-53.2dB. When power supply voltage changes from 1.7V to 2.5V, the output voltage deviation of BGR is only 617.6μV.

Single Inductor Bipolar Outputs DC-DC Converter with Current Mode Control Circuit

2013 ◽  
Vol 534 ◽  
pp. 220-226 ◽  
Author(s):  
Nobukazu Takai ◽  
Takashi Okada ◽  
Kenji Takahashi ◽  
Hajime Yokoo ◽  
Shunsuke Miwa ◽  
...  
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Process ◽  
Power Supply Voltage ◽  
Negative Power ◽  
Current Mode Control ◽  
Mode Control ◽  
Digital Still Camera ◽  
Simulation Results

Mobile equipment such as organic-EL display, digital still camera and so on re-quire both positive and negative power supply voltage to obtain high quality. Single InductorMultiple-Output (SIMO) DC-DC converter can provide a pair of positive and negative outputvoltages with only one external inductor. This paper describes SIMO DC-DC Converter usingproposed current-mode control (CMC) circuit. The proposed CMC circuit realizes high responsespeed for the change of load current. Spectre simulations with 0.18m CMOS process parameterare performed to verify the validity of the proposed converter. The simulation results indicatethat the proposed converter has higher response time compared with conventional converter.

Design of CMOS Sawtooth Wave Oscillator for Switching Power Supply

2014 ◽  
Vol 960-961 ◽  
pp. 1268-1271
Author(s):  
Zhu Lei Shao
Keyword(s):  
Power Supply ◽  
Oscillation Frequency ◽  
Supply Voltage ◽  
Effect Of Temperature ◽  
Maximum Deviation ◽  
Switching Power Supply ◽  
Power Supply Voltage ◽  
Sawtooth Wave ◽  
Switching Power ◽  
Wave Oscillator

Based on the CMOS technology, the sawtooth wave oscillator used in switching power supply is designed. In the condition of 27 °C and 4 V power supply voltage, the oscillation frequency of sawtooth wave oscillator is 246.61 KHz. The oscillation frequency of sawtooth wave oscillator changes between 245.94 KHz and 247.89 KHz when the power supply voltage changes between 3V and 6V. The maximum deviation is ±0.52%. From the experimental results, the sawtooth wave oscillator has good linearity, the effect of temperature and power supply to the oscillation frequency of sawtooth wave oscillator is very little. The CMOS sawtooth wave oscillator is suitable for switching power supply.

Integral Type Multi-Ramp for Single-Slope ADC

2013 ◽  
Vol 303-306 ◽  
pp. 1908-1912 ◽  
Author(s):  
Nan Lyu ◽  
Ning Mei Yu ◽  
He Jiu Zhang
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Supply Voltage ◽  
High Accuracy ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Voltage Reference ◽  
Integral Type ◽  
Power Supply Voltage ◽  
The One

This paper presents a integral type Multi-ramp architecture apply to MRSS ADC (Multiple-ramp single-slope ADC).On the one hand to improve the capacitance mismatch by change voltage reference, On the other hand to reduced the power consumption greatly. Implemented in the GSMC 180nm 2P4M CMOS process, in the power supply voltage of 1.8 V, 11-bit resolution, 10 MHZ sampling frequency, the result of max power consumption is 1.33mW of single unit .The DNL < 0.1LSB and max INL < 0.49LSB .The Multi-ramp achieved requirements for high speed and high accuracy MRSS ADC.

scholarly journals Design techniques for low-voltage analog integrated circuits

2017 ◽  
Vol 68 (4) ◽  
pp. 245-255 ◽  
Author(s):  
Matej Rakús ◽  
Viera Stopjaková ◽  
Daniel Arbet
Keyword(s):  
Integrated Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Building Blocks ◽  
Cmos Process ◽  
Mos Transistors ◽  
Power Supply Voltage ◽  
Current Mirrors ◽  
Moderate Inversion ◽  
Design Techniques

AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

The Design of Bandgap Reference Based on Empyrean Aether Software

2014 ◽  
Vol 687-691 ◽  
pp. 3489-3493
Author(s):  
Wei Qu ◽  
Li Mei Hou ◽  
Xiao Xin Sun ◽  
Jing Yu Sun ◽  
Liang Yu Li
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
Design Method ◽  
Reference Voltage ◽  
Voltage Source ◽  
Reference Source ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Power Supply Voltage ◽  
Reference Voltage Source

A high-performance bandgap reference voltage source design method is proposed in this paper, according to the shortcomings of traditional bandgap reference voltage source. This method combined CSMC 0.35μm CMOS process with Aether software technology, enabling to improve the bandgap reference source op amp performance and take into account accuracy and stability of the system. From the experimental results: this bandgap reference voltage source output voltage has changed about 63 mV when the temperature varied from to , and the line regulator is 0.4mV/V when the power supply voltage varied from 3.2V to 3.3V. This system has advantages of high accuracy and good stability.

2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations

2019 ◽  
Vol 29 (06) ◽  
pp. 2050088
Author(s):  
Chua-Chin Wang ◽  
Zong-You Hou ◽  
Yu-Lin Deng ◽  
U-Fat Chio ◽  
Wei Wang
Keyword(s):  
Threshold Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Output Buffer ◽  
Slew Rate ◽  
Output Stage ◽  
Detection Mechanism ◽  
Static Power ◽  
Low Threshold ◽  
28 Nm

A 2[Formula: see text]VDD CMOS output buffer with process, voltage and leakage (PVL) detection mechanism is proposed such that slew rate is auto-adjusted to reduce the variations at different corners. To boost the driving current, low threshold voltage transistors are used instead of devices with typical threshold voltage in the driving transistor of output stage. More importantly, to prevent large leakage of those large low threshold voltage devices, leakage detection resistors are added at the gates of the always-on low threshold voltage transistors to clamp the leakage. The static power consumption is reduced when it is not activated. Another feature of the proposed design is that the gate-oxide leakage is also reduced by lengthening the driving transistors. Besides, all biases in the proposed design are generated from bandgap circuits such that not only is the variation caused by temperature drifting reduced, the area overhead and power dissipation are also minimized. The proposed design is carried out by using 28-nm CMOS process. The data rate proved by physical measurement is proved to be 2.0[Formula: see text]GHz given 1.8/1.05[Formula: see text]V supply voltage, namely, VDD or 2[Formula: see text]VDD, when the proposed PVL detection as well as the compensation circuitry are activated.

scholarly journals Current Input Pixel-Level ADC with High SNR and Wide Dynamic Range for a Microbolometer

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2354
Author(s):  
Jeongho Lee ◽  
Ilku Nam ◽  
DooHyung Woo
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Signal To Noise Ratio ◽  
Integration Time ◽  
Cmos Process ◽  
Readout Circuit ◽  
Power Supply Voltage ◽  
Analog To Digital ◽  
Current Input ◽  
Cell Circuit

A readout circuit incorporating a pixel-level analog-to-digital converter (ADC) is studied for two-dimensional medium wavelength infrared microbolometer arrays. The signal-to-noise ratio (SNR) and charge handling capacity of the unit cell circuit are improved by using the current input pixel-level ADC. The charge handling capacity of the integrator is appropriately extended to maximize the integration time regardless of the magnitude of the input current and low power supply voltage. The readout circuit was fabricated using a 0.35-μm 2-poly 4-metal CMOS process for a 640 × 512 array with a pixel size of 40 μm × 40 μm. The peak SNR and dynamic range are 77.1 and 80.1 dB, respectively, with a power consumption of 0.62 μW per pixel.

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