INTEGRATED 60 GHZ ANTENNA, LNA AND FAST ADC ARCHITECTURE FOR EMBEDDED SYSTEMS WITH WIRELESS GBIT CONNECTIVITY

With reference to an architecture for the full integration of a 60 GHz receiver in embedded systems with wireless gigabit connectivity, the paper presents the design of key building blocks such as: on-chip antenna, low noise amplifier (LNA) and a time-interleaved fast A/D converter (ADC) with AMBA AXI interface towards the digital baseband part. With respect to the state of the art the co-design of the on-chip antenna with the LNA, and the fast ADC architecture realized as a time-interleaved array of threshold-configuring SAR channels, represent new solutions optimized in terms of power consumption. Complexity and performance results in a 65-nm CMOS SOI technology, suitable also for digital systems integration, are presented. The performance and complexity results of the designed antenna, LNA and ADC are integrated in a system level simulator with those obtained by adopting known solutions for other receiver blocks (mixer, IF and baseband amplifiers and filters, frequency synthesizer) thus estimating the performance achievable with a whole 60 GHz receiver and digitization sub-system macrocell. The system-level estimated performances confirm the feasibility of a full-integrated receiver supporting short-range High Definition (HD) connectivity of several Gb/s with a Signal-to-Noise-Ratio compliant with WiGig and Wireless HD new standardization initiatives.

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A 240-GHz circularly polarized FMCW radar based on a SiGe transceiver with a lens-coupled on-chip antenna

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078715000379 ◽

2015 ◽

Vol 7 (3-4) ◽

pp. 415-423 ◽

Cited By ~ 8

Author(s):

K. Statnikov ◽

J. Grzyb ◽

N. Sarmah ◽

S. Malz ◽

B. Heinemann ◽

...

Keyword(s):

Continuous Wave ◽

Building Blocks ◽

Low Noise ◽

Frequency Multiplier ◽

Center Frequency ◽

Radiated Power ◽

Wave Radar ◽

Compact Size ◽

On Chip Antenna ◽

On Chip

A 240-GHz monostatic circular polarized SiGe frequency-modulated continuous wave radar system based on a transceiver chip with a single on-chip antenna is presented. The radar transceiver front-end is implemented in a low-cost 0.13 µm SiGe HBT technology version with cut-off frequencies fT/fmaxof 300/450 GHz. The transmit block comprises a wideband ×16 frequency multiplier chain, a three-stage PA, while the receive block consists of a low-noise amplifier, a fundamental quadrature down-conversion mixer, and a three-stage PA to drive the mixer. A differential branch-line coupler and a differential dual-polarized on-chip antenna are added on-chip to realize a fully integrated radar transceiver. All building blocks are implemented fully differential. The use of a single antenna in the circular polarized radar transceiver leads to compact size and high sensitivity. The measured peak-radiated power from the Si-lens equipped radar module is +11 dBm (equivalent isotropically radiated power) at 246 GHz and noise figure is 21 dB. The characterization bandwidth of the radar transceiver is 60 GHz around the center frequency of 240 GHz, and the simulated Tx-to-Rx leakage is below −20 dB from 230 to 260 GHz. After system calibration the resolution of the system to distinguish between two targets at different distance of 3.65 mm is achieved, which is only 21% above the theoretical limit.

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A 60-GHz on-chip antenna using standard 0.18μm CMOS technology

2014 Joint IEEE International Symposium on the Applications of Ferroelectric, International Workshop on Acoustic Transduction Materials and Devices & Workshop on Piezoresponse Force Microscopy ◽

10.1109/isaf.2014.6918107 ◽

2014 ◽

Author(s):

Ning Wang ◽

Peng Gao ◽

Kai Kang

Keyword(s):

Cmos Technology ◽

60 Ghz ◽

On Chip Antenna ◽

On Chip

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60-GHz CMOS artificial magnetic conductor on-chip 2×2 monopole - antenna phased array RF receiving system with integrated variable-gain low-noise amplifier and phase shifter

2014 IEEE MTT-S International Microwave Symposium (IMS2014) ◽

10.1109/mwsym.2014.6848485 ◽

2014 ◽

Author(s):

Yi Wu ◽

Shih-Chiao Huang ◽

Chun-Han Yu ◽

Wen-Yi Ruan ◽

Huey-Ru Chuang

Keyword(s):

Phase Shifter ◽

Phased Array ◽

Low Noise ◽

Low Noise Amplifier ◽

Monopole Antenna ◽

60 Ghz ◽

Magnetic Conductor ◽

Variable Gain ◽

Noise Amplifier ◽

On Chip

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A 60-GHZ differential-fed circularly polarized on-chip antenna based on 0.18μm COMS technology with AMC structure

IET International Radar Conference 2015 ◽

10.1049/cp.2015.1001 ◽

2015 ◽

Cited By ~ 1

Author(s):

L. Wang ◽

W.Z. Sun

Keyword(s):

60 Ghz ◽

Circularly Polarized ◽

On Chip Antenna ◽

On Chip

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Optimized System-Level Design Methods for NoC-Based Many Core Embedded Systems

Advances in Systems Analysis, Software Engineering, and High Performance Computing - Handbook of Research on Embedded Systems Design ◽

10.4018/978-1-4666-6194-3.ch007 ◽

2014 ◽

pp. 150-179

Author(s):

Haoyuan Ying ◽

Klaus Hofmann ◽

Thomas Hollstein

Keyword(s):

Embedded Systems ◽

Design Optimization ◽

Optimization Methods ◽

Design Methods ◽

System Level ◽

System Level Design ◽

Level Design ◽

On Chip ◽

Many Core

Due to the growing demand on high performance and low power in embedded systems, many core architectures are proposed the most suitable solutions. While the design concentration of many core embedded systems is switching from computation-centric to communication-centric, Network-on-Chip (NoC) is one of the best interconnect techniques for such architectures because of the scalability and high communication bandwidth. Formalized and optimized system-level design methods for NoC-based many core embedded systems are desired to improve the system performance and to reduce the power consumption. In order to understand the design optimization methods in depth, a case study of optimizing many core embedded systems based on 3-Dimensional (3D) NoC with irregular vertical link distribution topology through task mapping, core placement, routing, and topology generation is demonstrated in this chapter. Results of cycle-accurate simulation experiments prove the validity and efficiency of the design methods. Specific to the case study configuration, in maximum 60% vertical links can be saved while maintaining the system efficiency in comparison to full vertical link connection 3D NoCs by applying the design optimization methods.

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