With reference to an architecture for the full integration of a 60 GHz receiver in embedded systems with wireless gigabit connectivity, the paper presents the design of key building blocks such as: on-chip antenna, low noise amplifier (LNA) and a time-interleaved fast A/D converter (ADC) with AMBA AXI interface towards the digital baseband part. With respect to the state of the art the co-design of the on-chip antenna with the LNA, and the fast ADC architecture realized as a time-interleaved array of threshold-configuring SAR channels, represent new solutions optimized in terms of power consumption. Complexity and performance results in a 65-nm CMOS SOI technology, suitable also for digital systems integration, are presented. The performance and complexity results of the designed antenna, LNA and ADC are integrated in a system level simulator with those obtained by adopting known solutions for other receiver blocks (mixer, IF and baseband amplifiers and filters, frequency synthesizer) thus estimating the performance achievable with a whole 60 GHz receiver and digitization sub-system macrocell. The system-level estimated performances confirm the feasibility of a full-integrated receiver supporting short-range High Definition (HD) connectivity of several Gb/s with a Signal-to-Noise-Ratio compliant with WiGig and Wireless HD new standardization initiatives.
A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications
