A WIDE-RANGE PROGRAMMABLE PULSE WIDTH CONTROLLER

2014 ◽  
Vol 23 (05) ◽  
pp. 1450075
Author(s):  
HADISEH BABAZADEH ◽  
ARASH ESMAILI ◽  
KHAYROLLAH HADIDI ◽  
ABDOLLAH KHOEI
Keyword(s):  
Duty Cycle ◽  
Power Supply ◽  
Pulse Width ◽  
Noise Source ◽  
Random Noise ◽  
Cmos Technology ◽  
Center Frequency ◽  
Maximum Speed ◽  
Frequency Range ◽  
Wide Range

A very simple, wide range and programmable pulse width controller or duty cycle corrector (DCC) is presented. Simulating the circuit in 0.35 μm Complementary MOSFET (CMOS) technology shows that the frequency range of the input signal can be within 250 MHz to 1.6 GHz, with a duty cycle of 30–70%. The proposed circuit generates an output signal with programmable duty cycle in the range of 30–70% with steps of 10% which could be extended to more steps by simple variations. The systematic peak-to-peak jitter at center frequency (1 GHz) is 1ps, while adding a random noise source of 5% of the power supply, increases it to 13 ps. the power consumption at maximum speed (1.6 GHz) is 4.9 mW. Monte Carlo simulations show maximum of 3.4% error at the 1.5 GHz input frequency and 70% output duty cycle.

scholarly journals A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology

2011 ◽  
Vol 8 (15) ◽  
pp. 1245-1251 ◽  
Author(s):  
Ching-Che Chung ◽  
Duo Sheng ◽  
Sung-En Shen
Keyword(s):  
Duty Cycle ◽  
Cmos Technology ◽  
Phase Alignment ◽  
Wide Range

Designing of a High Voltage Power Supply for Electrospinning Apparatus Using a High Voltage Flyback Transformer (HVFBT)

2015 ◽  
Vol 771 ◽  
pp. 145-148 ◽  
Author(s):  
Muhammad Miftahul Munir ◽  
Dian Ahmad Hapidin ◽  
Khairurrijal
Keyword(s):  
High Voltage ◽  
Duty Cycle ◽  
Power Supply ◽  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Experimental Results ◽  
High Voltage Power Supply ◽  
Electrospinning Technique ◽  
The World

Research on nanofiber materials is actively done around the world today. Various types of nanofibers have been synthesized using an electrospinning technique. The most important component when synthesizing nanofibers using the electrospinning technique is a DC high voltage power supply. Some requirements must be fulfilled by the high voltage power supply, i.e., it must be adjustable and its output voltage reaches tens of kilovolts. This paper discusses the design and development of a high voltage power supply using a diode-split transformer (DST)-type high voltage flyback transformer (HVFBT). The DST HVFBT was chosen because of its simplicity, compactness, inexpensiveness, and easiness of finding it. A pulse-width modulation (PWM) circuit with controlling frequency and duty cycle was fed to the DST HVFBT. The high voltage power supply was characterized by the frequency and duty cycle dependences of its output voltage. Experimental results showed that the frequency and duty cycle affect the output voltage. The output voltage could be set from 1 to 18 kV by changing the duty cycle. Therefore, the nanofibers could be synthesized by employing the developed high voltage power supply.

Design of a Digital Pulse Frequency Mode for the DC-DC Converter

2013 ◽  
Vol 411-414 ◽  
pp. 1649-1653
Author(s):  
Xin Lei ◽  
Jun Deng ◽  
Yan Lin Zhang ◽  
Huang Xu ◽  
Xiao Zong Huang ◽  
...  
Keyword(s):  
Duty Cycle ◽  
Pulse Width ◽  
Classical Model ◽  
Cmos Technology ◽  
Pulse Frequency ◽  
Frequency Mode ◽  
Light Load ◽  
Digital Pulse ◽  
Simulation Results ◽  
External Clock

The classical model in digital DC-DC converter is digital pulse width mode (DPWM), but the digital pulse frequency mode (DPFM) is very important in DC-DC converter with light load. This paper presents the different application environments and the effect between the two modes. There are two common different DPFM structures analyzed in this paper. And a novel DPFM circuit is proposed, which needs only external clock, not affected by the duty cycle of the clock. The circuit and layout are designed with 0.13um CMOS technology. The simulation results of the circuit meet the requirements of design.

A Novel Single Source Multiple Output Converter Integrating Buck-Boost and Fly Back Yopology for SMPS Applications

2017 ◽  
Vol 8 (3) ◽  
pp. 733 ◽  
Author(s):  
A. Kalirasu
Keyword(s):  
Duty Cycle ◽  
Power Supply ◽  
Output Voltage ◽  
Pi Controller ◽  
Single Source ◽  
Matlab Simulink ◽  
Boost Converters ◽  
Wide Range ◽  
Input Source ◽  
Switched Mode Power Supply

<p>This paper presents a novel single DC input source and multiple DC output suitable for switched mode power supply (SMPS) applications integrating interleaved boost and sepic converter with fly back topology. The proposed converter can be remodeled for any required output voltage power supply without changing hardware structure because wide range of output voltage can be obtained using sepic and boost converters by changing duty cycle command by implementing a simple voltage input pi controller. Conventional fly back topology is added to interleaved circuit to produce desired dc output voltage this voltage can be controlled by choosing turns ratio of fly back transformer. The proposed multi output DC converter is simulated in MATLAB/Simulink environment and results are presented for verifying merits of the converter.</p>

A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks

2015 ◽  
Vol 24 (07) ◽  
pp. 1550109
Author(s):  
Meilin Wan ◽  
Zhenzhen Zhang ◽  
Wang Liao ◽  
Kui Dai ◽  
Xuecheng Zou
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Single Phase ◽  
Cmos Technology ◽  
Operating Frequency ◽  
Low Power Consumption ◽  
Frequency Range ◽  
Differential Input ◽  
Operating Frequency Range ◽  
Simulation Results

A dual-modulus prescaler (divide-by-2/3) using complementary clocking NMOS-like blocks is presented in this paper. The prescaler can work properly for both differential and single phase input clocks. For differential input clocks, the prescaler achieves not only high operating frequency but also low power consumption since it consists of only five NMOS-like blocks. For single phase input clock, the operating frequency range is further expanded by utilizing a complementary clocks generator. Simulation results show that, in 180-nm standard CMOS technology, the proposed prescaler achieves operating frequency range of 1.7–9.0 GHz for differential input clocks and 0.5–10.2 GHz for single phase input clock. And the maximum power consumption from 1.8 V power supply is 0.92 mW and 1.32 mW for differential and single phase input clocks respectively.

scholarly journals PERANCANGAN FLYBACK CONVERTER UNTUK CATU DAYA DRIVER MOTOR BLDC ( BRUSHLESS DIRECT CURRENT )

Foristek ◽  
2019 ◽  
Vol 9 (2) ◽  
Author(s):  
Agus Mahendra ◽  
Sapril Sapril ◽  
Maryantho Masarrang
Keyword(s):  
Direct Current ◽  
Duty Cycle ◽  
Power Supply ◽  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Modulation Method ◽  
Flyback Converter ◽  
Direct Current Motor ◽  
Brushless Direct Current Motor

Flyback Converter is an electronic circuit that can increase the output voltage value, the voltage value can be adjusted by changing the value of the duty cycle. This Flyback Converter will be controlled by the Pulse Width Modulation method as the output voltage setting and this research is equipped with a feedback function as monitoring and control of Input Pulse Width Modulation. This designed flyback converter aims to provide an isolated power supply as a power source for Brushless Direct Current Motor drivers, and this research was conducted to analyze how much power the flyback converter can produce to be able to supply Brushless Direct Current Motor drivers. The results of the analysis obtained in the research Design of flyback converter for power supply of BLDC (Brushless Direct Current) motor driver that is flyback converter is given an input voltage of 31 VDC and output voltage of 15 VDC, rheostat load with a capacity of 39 Ohm, a frequency of 31 KHz in the form of a box wave duty cycle reaches 70%. Flyback converter designed to produce maximum power of 49.6 watts on 70% duty cycle testing.

scholarly journals Systems mutual loadings of traction asynchronous cars

2019 ◽  
Vol 294 ◽  
pp. 05009
Author(s):  
Andriy Afanasov ◽  
Oleksandr Shapovalov ◽  
Maryna Voitenko
Keyword(s):  
Power Supply ◽  
Power Efficiency ◽  
Reactive Power ◽  
Capital Expenditure ◽  
Wide Frequency Range ◽  
Electrical Machines ◽  
Rolling Stock ◽  
Frequency Range ◽  
Wide Range ◽  
High Level

The review of methods of post-repair tests of traction asynchronous motors under conditions of locomotive depot is carried out.The necessity of introducing special stands for post-repair tests is shown in order to improve their quality, reduce the number of failures of service equipment, improve safety of the railway transport. Let’s consider a question of power supply of the research asynchronous engine in wide frequency range and also a possibility of creation of the universal stand for testing important asynchronous engines of the electrorolling stock. Survey of possible versions of the scheme mutual loadings of asynchronous electrical machines which can be used for testing traction asynchronous engines of the rolling stock is executed. Such systems can be constructed both with use of the static converter of frequency, and without it. The given short characteristic of each alternative, certain advantages and shortcomings of each of system options. It is shown that systems with use of static converters of frequency differ in high power efficiency, allow to carry out tests in the wide frequency range of power supply, however have higher prime cost. Schemes without converters of frequency differ in smaller power efficiency, impossibility to carry out tests in the wide range of frequency of power supply, high level of consumption of reactive power . The results of the carried-out analysis can be used when choosing rational option of a system mutual loadings of asynchronous electric motors which will differ in higher functionality and power efficiency. Use of such systems will allow to lower capital expenditure for creation new and modernization of traction electrical machines that exist at the station for test.

A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology

2019 ◽  
Vol 29 (09) ◽  
pp. 2050142
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Charge Pump ◽  
Cmos Technology ◽  
Wide Frequency Range ◽  
Phase Detector ◽  
Total Power ◽  
Control Voltage ◽  
Frequency Range ◽  
Wide Range ◽  
Low Jitter

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6[Formula: see text]GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-[Formula: see text][Formula: see text]m CMOS technology with supply voltage of 1.8[Formula: see text]V. The output clocks with cycle-to-cycle jitter of 2.13[Formula: see text]ps at 1.6[Formula: see text]GHz. The phase noise of VCO is [Formula: see text]137[Formula: see text]dBc/Hz at an offset of 100[Formula: see text]MHz and total power consumed by the proposed PLL is 2.63[Formula: see text]mW at 1.6[Formula: see text]GHz.

scholarly journals Pulse width control loop as a duty cycle corrector

2004 ◽  
Vol 1 (2) ◽  
pp. 215-226 ◽  
Author(s):  
Goran Jovanovic ◽  
Mile Stojcev
Keyword(s):  
Duty Cycle ◽  
Pulse Width ◽  
High Speed ◽  
Pulse Generator ◽  
Building Blocks ◽  
Cmos Process ◽  
Control Loop ◽  
Saturation Region ◽  
Wide Range ◽  
Charge Pump Circuit

The clock distribution and generation circuitry forms a critical component of current synchronous digital systems. A digital system?s clocks must have not only low jitter, low skew, but also well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital [8]. In this paper, we propose a pulse width control loop referred as MPWCL (modified pulse width control loop) that adopts the same architecture as the conventional PWCL, but with a new pulse generator and new charge pump circuit as a constituent of the duty cycle detector. Thanks to using new building blocks the proposed pulse width control loop can control the duty cycle in a wide range, and what is more important it becomes operative in saturation region too, what provides conditional for fast locking time. For 1.2 ?m double-metal double-poly CMOS process with Vdd = 5 V and operating frequency of 133 MHz, results of SPICE simulation show that the duty cycle can be well controlled in the range from 20 % up to 80 % if the loop parameters are properly chosen.

scholarly journals Current mode pulse width modulation/pulse position modulation based on phase lock loop

2017 ◽  
Vol 68 (3) ◽  
pp. 180-187
Author(s):  
Pichet Wisartpong ◽  
Vorapong Silaphan ◽  
Sunee Kurutach ◽  
Paramote Wardkein
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Phase Lock Loop ◽  
Center Frequency ◽  
Loop Filter ◽  
Chip Area ◽  
Fully Integrated

Abstract In this paper, the fully integrated CMOS current mode PLL with current input injects at the place of input or output of the loop filter without summing amplifier circuit. It functions as PPM and PWM circuit is present. In addition, its frequency response is an analysis which electronic tuning BPF and LPF are obtained. The proposed circuit has been designed with 0.18 μm CMOS technology. The simulation results of this circuit can be operated at 2.5 V supply voltage, at center frequency 100 MHz. The linear range of input current can be adjusted from 43 μA to 109 μA, and the corresponding duty cycle of pulse width output is from 93% to 16% and the normalized pulse position is from 0.93 to 0.16. The power dissipation of this circuit is 4.68 mW with the total chip area is 28 μm × 60 μm.

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