Enhancing a 32-Bit Processor Core with Efficient Cryptographic Instructions

2015 ◽  
Vol 24 (10) ◽  
pp. 1550158 ◽  
Author(s):  
Noura Benhadjyoussef ◽  
Wajih Elhadjyoussef ◽  
Mohsen Machhout ◽  
Rached Tourki ◽  
Kholdoun Torki
Keyword(s):  
Power Consumption ◽  
Random Number ◽  
Random Number Generator ◽  
Instruction Set ◽  
Embedded Processor ◽  
Processor Core ◽  
Cryptographic Algorithms ◽  
Instruction Set Extensions ◽  
Types Of Instruction ◽  
Constrained Devices

Embedded processor is often expected to achieve a higher security with good performance and economical use of resource. However, the choice regarding the best solution for how cryptographic algorithms are incorporated in processor core is one of the most challenging assignments a designer has to face. This paper presents an inexpensive instruction set extensions (ISE) of efficient cryptographic algorithms on 32-bit processors assuring various types of instruction (public/private key cryptography, random number generator (RNG) and secure hash function (SHF)). These extensions provide hardware instructions that implement a full algorithm in a single instruction. Our enhanced LEON2 SPARC V8 core with cryptographic ISE is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40-nm technology. The total area of the resulting chip is about 1.93 mm2 and the estimated power consumption of the chip is 16.3 mW at 10 MHz. Hardware cost and power consumption evaluation are provided for different clock frequencies and the achieved results show that our circuit is able to be arranged in many security constrained devices.

scholarly journals TRNGs from Pre-Formed ReRAM Arrays

Cryptography ◽  
2021 ◽  
Vol 5 (1) ◽  
pp. 8
Author(s):  
Bertrand Cambou ◽  
Donald Telesca ◽  
Sareh Assiri ◽  
Michael Garrett ◽  
Saloni Jain ◽  
...  
Keyword(s):  
Random Number ◽  
Random Number Generator ◽  
Random Access ◽  
Random Number Generators ◽  
Cryptographic Algorithms ◽  
Cryptographic Keys ◽  
Low Levels ◽  
Stochastic Properties ◽  
Pseudo Random Number Generator ◽  
Number Of Cells

Schemes generating cryptographic keys from arrays of pre-formed Resistive Random Access (ReRAM) cells, called memristors, can also be used for the design of fast true random number generators (TRNG’s) of exceptional quality, while consuming low levels of electric power. Natural randomness is formed in the large stochastic cell-to-cell variations in resistance values at low injected currents in the pre-formed range. The proposed TRNG scheme can be designed with three interconnected blocks: (i) a pseudo-random number generator that acts as an extended output function to generate a stream of addresses pointing randomly at the array of ReRAM cells; (ii) a method to read the resistance values of these cells with a low injected current, and to convert the values into a stream of random bits; and, if needed, (iii) a method to further enhance the randomness of this stream such as mathematical, Boolean, and cryptographic algorithms. The natural stochastic properties of the ReRAM cells in the pre-forming range, at low currents, have been analyzed and demonstrated by measuring a statistically significant number of cells. Various implementations of the TRNGs with ReRAM arrays are presented in this paper.

scholarly journals A Lightweight BCH Code Corrector of TRNG with Measurable Dependence

2019 ◽  
Vol 2019 ◽  
pp. 1-11
Author(s):  
Hojoong Park ◽  
Yongjin Yeom ◽  
Ju-Sung Kang
Keyword(s):  
Linear Code ◽  
Random Number ◽  
Random Number Generator ◽  
The Other ◽  
Bch Code ◽  
Compression Rate ◽  
Number Generator ◽  
Von Neumann ◽  
Other Hand ◽  
Cryptographic Algorithms

We propose a new lightweight BCH code corrector of the random number generator such that the bitwise dependence of the output value is controllable. The proposed corrector is applicable to a lightweight environment and the degree of dependence among the output bits of the corrector is adjustable depending on the bias of the input bits. Hitherto, most correctors using a linear code are studied on the direction of reducing the bias among the output bits, where the biased input bits are independent. On the other hand, the output bits of a linear code corrector are inherently not independent even though the input bits are independent. However, there are no results dealing with the independence of the output bits. The well-known von Neumann corrector has an inefficient compression rate and the length of output bits is nondeterministic. Since the heavy cryptographic algorithms are used in the NIST’s conditioning component to reduce the bias of input bits, it is not appropriate in a lightweight environment. Thus we have concentrated on the linear code corrector and obtained the lightweight BCH code corrector with measurable dependence among the output bits as well as the bias. Moreover, we provide some simulations to examine our results.

scholarly journals Design of Pseudo Random Number Generator using Linear Feedback Shift Register

2019 ◽  
Vol 9 (2) ◽  
pp. 1956-1965 ◽  
Keyword(s):  
Information Technology ◽  
Random Number ◽  
Random Number Generator ◽  
Shift Register ◽  
Linear Feedback Shift Register ◽  
Linear Feedback ◽  
Number Generator ◽  
Cryptographic Algorithms ◽  
Feedback Shift Register ◽  
Pseudo Random Number Generator

Nowadays security has become a great concern in the field of computer science and information technology. In order to protect data from unintended users and to achieve a desirable level of security, several cryptographic algorithms based on various technology have been proposed. Linear Feedback Shift Register (LFSR) may play an important role in the design of such cryptographic algorithms. LFSR based cryptographic algorithms are often lightweight in nature and are more suitable for resource constraining devices. In this paper we present a detailed analysis of LFSR and design of LFSR to implement cryptographic algorithms.

scholarly journals Middle Square Method Analysis of Number Pseudorandom Process

2020 ◽  
Vol 4 (2) ◽  
pp. 35
Author(s):  
Arif Budiman ◽  
Efori Bulolo ◽  
Imam Saputra
Keyword(s):  
Data Collection ◽  
Random Number ◽  
Random Number Generator ◽  
Random Numbers ◽  
Number Generator ◽  
Cryptographic Algorithms ◽  
Mathematical Formulas ◽  
Method Analysis

Random numbers can be generated from a calculation of mathematical formulas. Such random numbers are often referred to as pseudo random numbers, random numbers are used for various algorithms, especially cryptographic algorithms such as AES, RSA, IDEA, GOST that require the use of Middle-Square Method random numbers which is very useful for adding research references to algorithms concerning random number generator and better understand how random numbers are generated using the Middle-Square Method algorithm. Both data collection and report making as for the objectives achieved in the form of understanding random numbers and knowing the algorithm process, compile a program designed to be used as an alternative to random numbers for various purposes, especially in cryptographic algorithms.

scholarly journals A Secure Random Number Generator with Immunity and Propagation Characteristics for Cryptography Functions

2021 ◽  
Vol 11 (17) ◽  
pp. 8073
Author(s):  
Rahul Saha ◽  
Ganesan Geetha ◽  
Gulshan Kumar ◽  
William J. Buchanan ◽  
Tai-hoon Kim
Keyword(s):  
Symmetric Functions ◽  
Random Number ◽  
Random Number Generator ◽  
Functional Requirements ◽  
Function Generator ◽  
Random Number Generators ◽  
Long Run ◽  
Cryptographic Algorithms ◽  
Block Based ◽  
Propagation Feature

Cryptographic algorithms and functions should possess some of the important functional requirements such as: non-linearity, resiliency, propagation and immunity. Several previous studies were executed to analyze these characteristics of the cryptographic functions specifically for Boolean and symmetric functions. Randomness is a requirement in present cryptographic algorithms and therefore, Symmetric Random Function Generator (SRFG) has been developed. In this paper, we have analysed SRFG based on propagation feature and immunity. Moreover, NIST recommended statistical suite has been tested on SRFG outputs. The test values show that SRFG possess some of the useful randomness properties for cryptographic applications such as individual frequency in a sequence and block-based frequency, long run of sequences, oscillations from 0 to 1 or vice-versa, patterns of bits, gap bits between two patterns, and overlapping block bits. We also analyze the comparison of SRFG and some existing random number generators. We observe that SRFG is efficient for cryptographic operations in terms of propagation and immunity features.

scholarly journals Random-telegraph-noise-enabled true random number generator for hardware security

2020 ◽  
Vol 10 (1) ◽  
Author(s):  
James Brown ◽  
Jian Fu Zhang ◽  
Bo Zhou ◽  
Mehzabeen Mehedi ◽  
Pedro Freitas ◽  
...  
Keyword(s):  
Power Consumption ◽  
Cyber Security ◽  
Random Number ◽  
Random Number Generator ◽  
Cmos Technology ◽  
Number Generator ◽  
Random Number Generators ◽  
True Random Number Generator ◽  
Telegraph Noise ◽  
Cmos Transistor

Abstract The future security of Internet of Things is a key concern in the cyber-security field. One of the key issues is the ability to generate random numbers with strict power and area constrains. “True Random Number Generators” have been presented as a potential solution to this problem but improvements in output bit rate, power consumption, and design complexity must be made. In this work we present a novel and experimentally verified “True Random Number Generator” that uses exclusively conventional CMOS technology as well as offering key improvements over previous designs in complexity, output bitrate, and power consumption. It uses the inherent randomness of telegraph noise in the channel current of a single CMOS transistor as an entropy source. For the first time multi-level and abnormal telegraph noise can be utilised, which greatly reduces device selectivity and offers much greater bitrates. The design is verified using a breadboard and FPGA proof of concept circuit and passes all 15 of the NIST randomness tests without any need for post-processing of the generated bitstream. The design also shows resilience against machine learning attacks performed by the LSTM neural network.

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