A Low-Voltage Low-Power Resistor-Based Current Mirror and Its Applications

2017 ◽  
Vol 26 (11) ◽  
pp. 1750180 ◽  
Author(s):  
Leila Safari ◽  
Shahram Minaei
Keyword(s):  
Output Voltage ◽  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Current Mirror ◽  
Output Impedance ◽  
High Cmrr ◽  
High Output Impedance

In this paper, a CMOS resistor-based current mirror (RBCM) aimed to be used in low-voltage applications is presented. The main features of the proposed current mirror are very low input voltage requirement (a few mV), low output voltage requirement, high output impedance and simple circuitry. The core structure of the proposed RBCM consists of three transistors (excluding bias circuitry) and two low value grounded resistors. The proposed circuit alleviates the need for cascode structures which are conventionally used to boost the output impedance and linearity. SPICE simulations using 0.18[Formula: see text][Formula: see text]m CMOS technology parameters under supply voltage of 0.9[Formula: see text]V are reported which show input and output voltage requirements of 40[Formula: see text]mV and 0.1[Formula: see text]V respectively, low THD of 1.2%, [Formula: see text] of 496[Formula: see text][Formula: see text], [Formula: see text] of 1[Formula: see text]M[Formula: see text], [Formula: see text]3[Formula: see text]dB bandwidth of 181[Formula: see text]MHz and power dissipation of 154[Formula: see text][Formula: see text]W. A high CMRR differential amplifier and a high performance current difference circuit as applications of the proposed RBCM are given. The proposed RBCM is very useful in tackling restrictions of modern technologies such as reduced supply voltage and transistors low intrinsic output impedance.

scholarly journals A design of low voltage OPAMP using split-length transistors

2014 ◽  
Vol 17 (1) ◽  
pp. 62-70
Author(s):  
Khanh Trung Le ◽  
Tu Trong Bui ◽  
Hung Duc Le ◽  
Kha Cong Pham
Keyword(s):  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Feedback Systems ◽  
Advanced Technique ◽  
Low Voltage Operation ◽  
Feedback Compensation ◽  
Indirect Feedback ◽  
Low Supply Voltage

In the paper, we present a design of a low voltage Operation Amplifier (OPAMP) circuit using split-length transistors. Indirect feedback compensation is an advanced technique used to stabilize the operation of an OPAMP. Cascode transistors are usually implemented for indirect feedback systems. However, these transistors are not suitable for low voltage design. In this study, we have taken advantage of split-length transistors and indirect feedback compensation technique to design a high performance OPAMP. As a result, the OPAMP operates not only at low supply voltage but also at high frequency. The OPAMP has been designed and fabricated in a 0.18um CMOS technology. This OPAMP achieves 100 dB gain, 90 MHz unity gain frequency and 60 degrees phase margin at 2 V supply voltage.

scholarly journals Low-voltage 0.35-/mi cmos wideband operational transconductance amplifier

2002 ◽  
Vol 15 (3) ◽  
pp. 361-369
Author(s):  
Lyes Bouzerara ◽  
Mohand Belaroussi
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Output Impedance ◽  
Power Supply Voltage ◽  
Gain Bandwidth ◽  
Current Mirrors ◽  
Transconductance Amplifier ◽  
Cascade Structure ◽  
Feedback Frequency ◽  
High Output Impedance

A low voltage CMOS wideband operational Tran conductance amplifier (OTA) using regulated cascade structure with an active positive feedback frequency-dependent current mirrors and feed forward techniques, is presented and analyzed. Such techniques stand as a powerful method of gain bandwidth, output impedance and phase margin enhancements. In this paper, an efficient implementation of a high output impedance current mirror is used in the design of an OTA by means of the regulated cascade circuits. This amplifier operates at ?1.25 V power supply voltage, exhibits a voltage gain of 68 dB, and provides a gain bandwidth product of 166 MHz. It drives a capacitive load of 1.6 pF and gives a power dissipation of 8.5 mW. The predicted performance is verified by simulations using HSPICE tool with 0.35 /itm CMOS TSMC parameters.

130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications

2017 ◽  
Vol 26 (08) ◽  
pp. 1740003 ◽  
Author(s):  
Daniel Arbet ◽  
Viera Stopjaková ◽  
Martin Kováč ◽  
Lukáš Nagy ◽  
Matej Rakús ◽  
...  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Variable Gain Amplifier ◽  
Voltage Range ◽  
Variable Gain ◽  
Wide Scale ◽  
Simulation Results ◽  
Low Supply Voltage

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide scale, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications. An additional circuit responsible for maintaining the linear-in-decibel gain dependency of the VGA is also addressed. The proposed circuit block avails arbitrary shaping of the curve characterizing the gain versus the controlling voltage dependency.

Fast-Transient-Response Low-Voltage Integrated, Interleaved DC–DC Converter for Implantable Devices

2019 ◽  
Vol 29 (01) ◽  
pp. 2050013
Author(s):  
Najmeh Cheraghi Shirazi ◽  
Abumoslem Jannesari ◽  
Pooya Torkzadeh
Keyword(s):  
Power Consumption ◽  
Transient Response ◽  
Output Voltage ◽  
Low Voltage ◽  
Charge Pump ◽  
Input Voltage ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Voltage Ripple ◽  
Body Biasing

A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[Formula: see text]mV and 20[Formula: see text]MHz clock frequency for 1[Formula: see text]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[Formula: see text]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[Formula: see text][Formula: see text]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[Formula: see text]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [Formula: see text][Formula: see text][Formula: see text]m for TBCCCP, [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP2 and [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP4.

A Compact High-Performance 10-bit 30-Channel OLED Driver Using Switched Capacitor Circuit for High-Linearity Application

2021 ◽  
pp. 2250013
Author(s):  
Neeru Agarwal ◽  
Neeraj Agarwal ◽  
Chih-Wen Lu
Keyword(s):  
Power Consumption ◽  
Output Voltage ◽  
High Speed ◽  
High Performance ◽  
Input Voltage ◽  
Cmos Technology ◽  
Settling Time ◽  
Switched Capacitor ◽  
Voltage Range ◽  
High Output Voltage

This work proposes a new OLED driver architecture with 10-bit segmented DAC and switched capacitor multiply-by-two circuit application. A 30-channel 10-bit switched capacitor driver chip prototype is implemented in 0.18-[Formula: see text]m CMOS technology. In this architecture, the achieved output range is 1.5–4.8[Formula: see text]V for an input range of 1.5–3.15[Formula: see text]V, which is suitable for OLED driver with different colors. This architecture is not only converting the digital input signal to analog output for the display panel but also giving amplified high output voltage range. In the segmented DAC, 6-bit coarse DAC and 4-bit fine DAC are used for the input voltage range 1.5–3.15[Formula: see text]V. In a conventional RDAC for the output voltage of 4.8[Formula: see text]V, it requires 2[Formula: see text] switches i.e., 14-bit RDAC for the same resolution. Hence, conventional RDAC driver is four times larger than the proposed innovative very compact and high speed 10-bit segmented DAC switched capacitor OLED driver. The new architecture drastically reduces the number of switches and complex metal routing which results in reduced power consumption and good settling time. In the proposed OLED driver, no extra buffer is required as switched capacitor op-amp is applied for the same purpose with a gain of more than one. This high-resolution design with small die area also improves the linearity and uniformity with low-power consumption. The post-simulated results show that the OLED driver exhibits the maximum DNL and INL of 0.03 LSB and [Formula: see text]0.06 LSB, respectively, with an LSB voltage of 3[Formula: see text]mV. The one-channel area is 0.586[Formula: see text]mm [Formula: see text] 0.017[Formula: see text]mm and the settling time is 4.25[Formula: see text][Formula: see text]s for 30[Formula: see text]k[Formula: see text] and 30[Formula: see text]pF driving load.

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