High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

2015 ◽  
Vol 24 (04) ◽  
pp. 1550057 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Two Stage ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Folded Cascode

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

A QFGMOS-Based gm-Boosted and Adaptively Biased Two-Stage Amplifier Offering Very High Gain and High Bandwidth

2021 ◽  
pp. 2250056
Author(s):  
Urvashi Bansal ◽  
Abhilasha Bakre ◽  
Prem Kumar ◽  
Devansh Yadav ◽  
Mohit Kumar ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Slew Rate ◽  
Two Stage ◽  
Adaptive Biasing ◽  
Unity Gain ◽  
High Bandwidth ◽  
Cmos Amplifier

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

A Low-Noise High-Gain Recycling Folded Cascode Operational Transconductance Amplifier Based on Gate Driven and Quasi-Floating Bulk Technique

2021 ◽  
Author(s):  
Roowz Saini ◽  
Kulbhushan Sharma ◽  
Rajnish Sharma
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Monte Carlo Analysis ◽  
High Gain ◽  
Low Noise ◽  
Operational Transconductance Amplifier ◽  
Sensor Applications ◽  
Transconductance Amplifier ◽  
Folded Cascode

Operational Transconductance Amplifier (OTA) is an important circuit block used in the design of filter, amplifiers and oscillators for various analog-mixed circuit systems. However, design of a low-noise, high-gain OTA with low-power consumption is a challenging task in CMOS technology owing to high-power requirements of OTA for emulating high gain. This paper represents the design of gate-driven quasi-floating bulk recycling folded cascode (GDQFB RFC) OTA which has been shown to provide low-noise operation, emulates high gain and draws very less power. The design utilizes the gate-driven quasi-floating bulk (GDQFB) technique on a recycling folded cascode structure, which enhances the transconductance of OTA and improves its performance. All the post-layout simulation results have been obtained in 0.18-[Formula: see text]m CMOS N-well technology using BSIM3V3 device models. The obtained results indicate very high gain of 100.4 dB, gain-bandwidth of 69[Formula: see text]kHz, phase margin of 51.9∘ with power consumption of 2.31[Formula: see text][Formula: see text]W from [Formula: see text][Formula: see text]V supply voltage. The input referred noise emulated by proposed OTA is 0.684, 0.21 and 0.0592[Formula: see text][Formula: see text]V/[Formula: see text]Hz @ 1[Formula: see text]Hz, 10[Formula: see text]Hz and 1[Formula: see text]kHz, respectively. The input common mode range and output voltage swing are found to be [Formula: see text] to 0.669[Formula: see text]V and [Formula: see text] to 0.610[Formula: see text]V, respectively. Corner simulations and Monte Carlo analysis have been performed to verify the robustness of the proposed OTA. The proposed OTA can be used in design of filters and amplifiers for bio-instruments, sensor applications, neural recording applications and human implants etc.

scholarly journals Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-11 ◽  
Author(s):  
Rida Assaad ◽  
Jose Silva-Martinez
Keyword(s):  
High Frequency ◽  
High Gain ◽  
Feed Forward ◽  
Operational Transconductance Amplifiers ◽  
Miller Compensation ◽  
Multistage Amplifiers ◽  
Dc Gain ◽  
Folded Cascode ◽  
Transconductance Amplifiers ◽  
Better Than

Feed-forward techniques are explored for the design of high-frequency Operational Transconductance Amplifiers (OTAs). For single-stage amplifiers, a recycling folded-cascode OTA presents twice the GBW (197.2 MHz versus 106.3 MHz) and more than twice the slew rate (231.1 V/s versus 99.3 V/s) as a conventional folded cascode OTA for the same load, power consumption, and transistor dimensions. It is demonstrated that the efficiency of the recycling folded-cascode is equivalent to that of a telescopic OTA. As for multistage amplifiers, a No-Capacitor Feed-Forward (NCFF) compensation scheme which uses a high-frequency pole-zero doublet to obtain greater than 90 dB DC gain, GBW of 325 MHz and better than phase margin is discussed. The settling-time- of the NCFF topology can be faster than that of OTAs with Miller compensation. Experimental results for the recycling folded-cascode OTA fabricated in TSMC 0.18 m CMOS, and results of the NCFF demonstrate the efficiency and feasibility of the feed-forward schemes.

Low Power Operational Transconductance Amplifier (OTA) with Enhanced DC Gain and Slew-Rate

2013 ◽  
Vol 411-414 ◽  
pp. 1645-1648
Author(s):  
Xiao Zong Huang ◽  
Lun Cai Liu ◽  
Jian Gang Shi ◽  
Wen Gang Huang ◽  
Fan Liu ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Current Mirror ◽  
Slew Rate ◽  
Operational Transconductance Amplifier ◽  
Theory Analysis ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Simulation Results

This paper presents a low-voltage differential operational transconductance amplifier (OTA) with enhanced DC gain and slew-rate. Based on the current mirror OTA topology, the optimization techniques are discussed in this work. The proposed structure achieves enhanced DC gain, unit gain frequency (UGF) and slew-rate (SR) with adding four devices. The design of the OTA is described with theory analysis. The OTA operates at the power supply of 1.8V. Simulation results for 0.18μm standard CMOS technology show that the DC gain increases from 60.6dB to 65dB, the UGF is optimized from 2.5MHz to 4.3MHz, the SR is enhanced from 0.88 V/μs to 4.8 V/μs with close power consumption dramatically.

LOW VOLTAGE, LOW POWER CHEBYSHEV FILTER IN 0.18 μm CMOS TECHNOLOGY

2013 ◽  
Vol 22 (07) ◽  
pp. 1350053 ◽  
Author(s):  
S. REKHA ◽  
T. LAXMINIDHI
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Transconductance Amplifier ◽  
Low Pass ◽  
Unity Gain ◽  
Design Centering ◽  
Low Supply Voltage

This paper presents an active-RC continuous time filter in 0.18 μm standard CMOS technology intended to operate on a very low supply voltage of 0.5 V. The filter designed, has a 5th order Chebyshev low pass response with a bandwidth of 477 kHz and 1-dB passband ripple. A low-power operational transconductance amplifier (OTA) is designed which makes the filter realizable. The OTA uses bulk-driven input transistors and feed-forward compensation in order to increase the Dynamic Range and Unity Gain Bandwidth, respectively. The paper also presents an equivalent circuit of the OTA and explains how the filter can be modeled using descriptor state-space equations which will be used for design centering the filter in the presence of parasitics. The designed filter offers a dynamic range of 51.3 dB while consuming a power of 237 μW.

A High Gain, 808MHz GBW Four-Stage OTA in 65nm CMOS

2019 ◽  
Vol 28 (11) ◽  
pp. 1950192
Author(s):  
Zhe Li ◽  
Rui Ma ◽  
Maliang Liu ◽  
Ruixue Ding ◽  
Zhangming Zhu
Keyword(s):  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Model Stability ◽  
Analysis And Design ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Compensation Technique ◽  
Layout Area ◽  
The Stability

A four-stage operational transconductance amplifier (OTA) with a novel compensation structure combining multipath [Formula: see text]-[Formula: see text] compensation and no capacitor feed-forward compensation is proposed in this paper. Based on the small-signal model, stability analysis and design consideration are carried out to demonstrate the stability of the compensation technique. To verify the effectiveness of the compensation scheme, the proposed OTA which drives a 2 pF capacitance, is simulated in TSMC 65[Formula: see text]nm 1.2[Formula: see text]V CMOS process, achieving 808[Formula: see text]MHz gain-bandwidth, 119[Formula: see text]dB DC gain, 585[Formula: see text]V/[Formula: see text]s slew rate (SR) and 6 ns 1% settling time. The circuit is operated at the single supply voltage of 1.2[Formula: see text]V with power consumption of 2.17[Formula: see text]mW and the layout area is 0.011[Formula: see text]mm2.

Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits

2016 ◽  
Vol 25 (11) ◽  
pp. 1650144 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
Gain Bandwidth ◽  
Class Ab ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Signal Path ◽  
Folded Cascode ◽  
Fast Settling ◽  
Current Shunt

In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.

scholarly journals Ultra-Low-Voltage Low-Power Bulk-Driven Quasi-Floating-Gate Operational Transconductance Amplifier

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Ziad Alsibai ◽  
Salma Bay Abo Dabbous
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Bias Current ◽  
Floating Gate ◽  
Operational Transconductance Amplifier ◽  
Transconductance Amplifier

A new ultra-low-voltage (LV) low-power (LP) bulk-driven quasi-floating-gate (BD-QFG) operational transconductance amplifier (OTA) is presented in this paper. The proposed circuit is designed using 0.18 μm CMOS technology. A supply voltage of ±0.3 V and a quiescent bias current of 5 μA are used. The PSpice simulation result shows that the power consumption of the proposed BD-QFG OTA is 13.4 μW. Thus, the circuit is suitable for low-power applications. In order to confirm that the proposed BD-QFG OTA can be used in analog signal processing, a BD-QFG OTA-based diodeless precision rectifier is designed as an example application. This rectifier employs only two BD-QFG OTAs and consumes only 26.8 μW.

scholarly journals MOCCCDTA-based Current Mode Tunable Universal Biquad Filter for Bluetooth Applications

2016 ◽  
Vol 6 (4) ◽  
pp. 1499
Author(s):  
Jyoti Sharma ◽  
Shantanu Chakraborty
Keyword(s):  
Active Element ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Biquad Filter ◽  
Transconductance Amplifier ◽  
Theoretical Predictions ◽  
Current Differencing Transconductance Amplifier ◽  
Mode Technique

<p>In the last decade, there has been much effort to reduce the supply voltage of electronic circuits due to the demand for portable and battery-powered equipment. Since a low-voltage operating circuit becomes necessary, the current-mode technique is ideally suited for this purpose more than the voltage-mode one. In this paper, performance of multi output current controlled current differencing transconductance amplifier (MOCCCDTA) is evaluated using 180nm, 90nm and 45nm CMOS technology. It is found that the 45nm CMOS-based<br />MOCCCDTA provides highest frequency i.e. 33GHz. Further a Universal biquad filter has been designed using a single MOCCCDTA as an active element and two capacitors. Filter offers high frequency in GHz. Tunability of all the filter outputs with respect to a bias current has been analyzed. The tunability of the filter circuit for Bluetooth applications is also shown in this work. The performances of MOCCCDTA circuit and Universal biquad filter are illustrated by HSPICE. The simulation results are found to be in agreement with the theoretical predictions.</p>

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