A Low-Power High-Linear Time-to-Digital Converter for Measuring R-R Intervals in ECG Signal Optimized by Neural Network and TLBO Algorithm

In this paper, a two-stage time interpolation time-to-digital converter (TDC) is proposed to achieve adequate resolution and wide dynamic range for measuring R-R intervals in QRS detection. The architecture is based on a coarse counter and a couple of two-stage interpolator circuit in order to improve the conversion linearity. The proposed TDC is modeled with the neural network, while the teacher–learner-based optimization algorithm (TLBO) is used to optimize the integral nonlinearity (INL) of the proposed TDC. The proposed optimization method shows a characteristic close to the ideal output of the TDC behavior over a wide input range. Using the achieved results of the TLBO algorithm simulation results using CADENCE VIRTUOSO and standard 180[Formula: see text]nm CMOS technology shows 1.2[Formula: see text]s dynamic range, 100[Formula: see text]ns resolution, 0.19[Formula: see text]mW power consumption and area of 0.16[Formula: see text]mm2. The proposed circuit can find application in biomedical engineering systems and other fields where long and accurate time interval measurement is needed.

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A CMOS Integrator-Based Clock-Free Time-to-Digital Converter for Home-Monitoring LiDAR Sensors

Sensors ◽

10.3390/s22020554 ◽

2022 ◽

Vol 22 (2) ◽

pp. 554

Author(s):

Ying He ◽

Sung Min Park

Keyword(s):

Power Dissipation ◽

Dynamic Range ◽

Home Monitoring ◽

Cmos Technology ◽

Digital Converter ◽

Detection Range ◽

Time To Digital Converter ◽

Fine Control ◽

Test Chips ◽

Total Test

This paper presents a nine-bit integrator-based time-to-digital converter (I-TDC) realized in a 180 nm CMOS technology for the applications of indoor home-monitoring light detection and ranging (LiDAR) sensors. The proposed I-TDC exploits a clock-free configuration so as to discard clock-related dynamic power consumption and some notorious issues such as skew, glitch, and synchronization. It consists of a one-dimensional (1D) flash TDC to generate coarse-control codes and an integrator with a peak detection and hold (PDH) circuit to produce fine-control codes. A thermometer-to-binary converter is added to the 1D flash TDC, yielding four-bit coarse codes so that the measured detection range can be represented by nine-bit digital codes in total. Test chips of the proposed I-TDC demonstrate the measured results of the 53 dB dynamic range, i.e., the maximum detection range of 33.6 m and the minimum range of 7.5 cm. The chip core occupies the area of 0.14 × 1.4 mm2, with the power dissipation of 1.6 mW from a single 1.2-V supply.

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Increasing a Resolution of Time to Digital Converter

Mokslas - Lietuvos ateitis ◽

10.3846/mla.2017.1041 ◽

2017 ◽

Vol 9 (3) ◽

pp. 318-323

Author(s):

Marijan Jurgo ◽

Romualdas Navickas

Keyword(s):

Delay Time ◽

Noise Level ◽

Delay Line ◽

Cmos Technology ◽

Phase Detector ◽

Quantization Noise ◽

Time Interval ◽

Digital Converter ◽

Technological Parameters ◽

Time To Digital Converter

Time to digital converter (TDC) is one of the main blocks of all-digital frequency synthesizer (FS), where it is used as phase detector. The output of TDC is digital, therefore it introduces quantization noise to the output of FS. The resolution of TDC has to be increased, to improve phase noise level at the output of FS. It can be achieved by improving CMOS technology or structure of the TDC. The simplest TDC is based on inverter delay line. Its resolution is inversely proportional to the time interval, which can be measured with such TDC, i.e. delay time of the inverter. Decreasing of this delay is essence of technological increasing of TDC’s resolution. In this work the dependency of inverter delay on technological parameters is shown and its value is calculated in 65 nm CMOS technology. Calculations show, that in this technology delay time of the inverter can vary from 7 ps to 54 ps. If the design is restricted to the usage of specific CMOS technology, in which inverter’s delay does not ensure needed noise level at the output of FS, structure of the TDC needs to be improved. The aim of this improvement is to measure time interval smaller than inverter’s delay. Some of the TDC structures, which can measure sub-inverter delay time, are reviewed in this work: TDC – Vernier delay line, TDC – 2D Vernier plane, stochastic, ring and multistage TDCs.

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A 9-bit body-biased vernier ring time-to-digital converter in 65 nm CMOS technology

2015 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2015.7168967 ◽

2015 ◽

Cited By ~ 3

Author(s):

Junjie Kong ◽

Liter Siek ◽

Chiang-Liang Kok

Keyword(s):

Cmos Technology ◽

Digital Converter ◽

Time To Digital Converter

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A Two-Stage Optimization Method for the Stencil Printing Process Based on Neural Network and Response Surface Method

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.156-157.10 ◽

2010 ◽

Vol 156-157 ◽

pp. 10-17 ◽

Cited By ~ 2

Author(s):

Er Shun Pan ◽

Yao Jin ◽

Zhao Mei ◽

Ying Wang

Keyword(s):

Neural Network ◽

Response Surface ◽

Response Surface Method ◽

Model Fitting ◽

Optimization Method ◽

Small Sample ◽

Two Stage ◽

Stencil Printing ◽

Printing Process ◽

Surface Method

A stencil printing process (SPP) optimization problem is studied in this paper. Due to the limitation that neural network requires a large number of samples for the accurate model fitting, a two-stage SPP optimization method is proposed. The design interval can be reduced with small sample by using neural network. In this reduced design interval , response surface method is adopted to obtain the accurate mathematical SPP model. The concept of confidence level is introduced to make the proposed model robust. An interactive method is used to solve the model. The proposed method is compared with the one-stage optimization method and the results show that the proposed method achieves a better performance on each objective.

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A 9 Bit, 3.6 ps Resolution Pipeline Time-to-Digital Converter

Journal of Circuits System and Computers ◽

10.1142/s0218126620501248 ◽

2019 ◽

Vol 29 (08) ◽

pp. 2050124

Author(s):

Farshad Goodarzi ◽

Siroos Toofan

Keyword(s):

Fine Structure ◽

Delay Line ◽

Supply Voltage ◽

Cmos Technology ◽

Digital Converter ◽

Time Intervals ◽

Wide Linear Range ◽

Time To Digital Converter ◽

Good Linearity ◽

Time Amplifier

This paper describes a 9-bit time-to-digital converter (TDC) with 3.6 ps resolution. The resolution of 3.6 ps is achieved using coarse and fine structure. The structure of the proposed two-step pipeline TDC is composed of a 4-bit coarse TDC (CTDC) based on delay line and a 5-bit fine TDC (FTDC) based on an SAR-CD algorithm where a Time Amplifier (TA) is used between them. Since TA amplifies the time intervals in different stages of delay line to achieve accurate gain with wide linear range. Therefore, the TDC has good linearity. The proposed TDC has Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) errors of 1.6 and 2.6 LSB, respectively. This TDC was designed in 0.18[Formula: see text][Formula: see text]m CMOS technology. Using a supply voltage of 1.8[Formula: see text]V, the proposed TDC consumes 1.88[Formula: see text]mW at 25 MS/s throughput.

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Radiation Assessment of a 15.6ps Single-Shot Time-to-Digital Converter in Terms of TID

Electronics ◽

10.3390/electronics8050558 ◽

2019 ◽

Vol 8 (5) ◽

pp. 558 ◽

Cited By ~ 3

Author(s):

Bjorn Van Bockel ◽

Jeffrey Prinzie ◽

Paul Leroux

Keyword(s):

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Ring Oscillator ◽

Oxide Semiconductor ◽

Single Shot ◽

Digital Converter ◽

Time To Digital Converter ◽

Pvt Variations ◽

Radiation Tolerant ◽

Radiation Measurements

This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS) technology. The TDC is based on a multipath pseudo differential ring oscillator with reduced phase delay, without the need for calibration or interpolation. The ring oscillator is placed inside a Phase Locked Loop (PLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation. Measurements to evaluate the performance of the TDC in terms of the total ionizing dose (TID) were done. Two different samples were irradiated up to a dose of 2.2 MGy SiO 2 while still maintaining a resolution of 15.6 ps. The TDC has a differential non-linearity (DNL) and integral non-linearity (INL) of 0.22 LSB rms and 0.34 LSB rms respectively.

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