A stochastic sampling time-to-digital converter with tunable 180–770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset

2013 ◽  
Author(s):  
James S. Tandon ◽  
Takahiro J. Yamaguchi ◽  
Satoshi Komatsu ◽  
Kunihiro Asada
Keyword(s):  
Dynamic Range ◽  
Sampling Time ◽  
Digital Converter ◽  
Stochastic Sampling ◽  
Time To Digital Converter

A Low-Power High-Linear Time-to-Digital Converter for Measuring R-R Intervals in ECG Signal Optimized by Neural Network and TLBO Algorithm

2018 ◽  
Vol 28 (02) ◽  
pp. 1950021
Author(s):  
B. Ghanavati ◽  
E. Abiri ◽  
M. R. Salehi ◽  
N. Azhdari
Keyword(s):  
Neural Network ◽  
Dynamic Range ◽  
Linear Time ◽  
Optimization Method ◽  
Cmos Technology ◽  
Time Interval ◽  
Digital Converter ◽  
Two Stage ◽  
Time To Digital Converter ◽  
Tlbo Algorithm

In this paper, a two-stage time interpolation time-to-digital converter (TDC) is proposed to achieve adequate resolution and wide dynamic range for measuring R-R intervals in QRS detection. The architecture is based on a coarse counter and a couple of two-stage interpolator circuit in order to improve the conversion linearity. The proposed TDC is modeled with the neural network, while the teacher–learner-based optimization algorithm (TLBO) is used to optimize the integral nonlinearity (INL) of the proposed TDC. The proposed optimization method shows a characteristic close to the ideal output of the TDC behavior over a wide input range. Using the achieved results of the TLBO algorithm simulation results using CADENCE VIRTUOSO and standard 180[Formula: see text]nm CMOS technology shows 1.2[Formula: see text]s dynamic range, 100[Formula: see text]ns resolution, 0.19[Formula: see text]mW power consumption and area of 0.16[Formula: see text]mm2. The proposed circuit can find application in biomedical engineering systems and other fields where long and accurate time interval measurement is needed.

scholarly journals A CMOS Integrator-Based Clock-Free Time-to-Digital Converter for Home-Monitoring LiDAR Sensors

Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 554
Author(s):  
Ying He ◽  
Sung Min Park
Keyword(s):  
Power Dissipation ◽  
Dynamic Range ◽  
Home Monitoring ◽  
Cmos Technology ◽  
Digital Converter ◽  
Detection Range ◽  
Time To Digital Converter ◽  
Fine Control ◽  
Test Chips ◽  
Total Test

This paper presents a nine-bit integrator-based time-to-digital converter (I-TDC) realized in a 180 nm CMOS technology for the applications of indoor home-monitoring light detection and ranging (LiDAR) sensors. The proposed I-TDC exploits a clock-free configuration so as to discard clock-related dynamic power consumption and some notorious issues such as skew, glitch, and synchronization. It consists of a one-dimensional (1D) flash TDC to generate coarse-control codes and an integrator with a peak detection and hold (PDH) circuit to produce fine-control codes. A thermometer-to-binary converter is added to the 1D flash TDC, yielding four-bit coarse codes so that the measured detection range can be represented by nine-bit digital codes in total. Test chips of the proposed I-TDC demonstrate the measured results of the 53 dB dynamic range, i.e., the maximum detection range of 33.6 m and the minimum range of 7.5 cm. The chip core occupies the area of 0.14 × 1.4 mm2, with the power dissipation of 1.6 mW from a single 1.2-V supply.

Note: All-digital pulse-shrinking time-to-digital converter with improved dynamic range

2016 ◽  
Vol 87 (4) ◽  
pp. 046104 ◽  
Author(s):  
Chun-Chi Chen ◽  
Chorng-Sii Hwang ◽  
Yi Lin ◽  
Guan-Hong Chen
Keyword(s):  
Dynamic Range ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Digital Pulse

scholarly journals A 13-Bit, 12-ps Resolution Vernier Time-to-Digital Converter Based on Dual Delay-Rings for SPAD Image Sensor

Sensors ◽  
2021 ◽  
Vol 21 (3) ◽  
pp. 743
Author(s):  
Zunkai Huang ◽  
Jinglin Huang ◽  
Li Tian ◽  
Ning Wang ◽  
Yongxin Zhu ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Single Photon ◽  
Image Sensor ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Digital Converter ◽  
Delay Element ◽  
Time To Digital Converter ◽  
Total Power Consumption

A three-dimensional (3D) image sensor based on Single-Photon Avalanche Diode (SPAD) requires a time-to-digital converter (TDC) with a wide dynamic range and fine resolution for precise depth calculation. In this paper, we propose a novel high-performance TDC for a SPAD image sensor. In our design, we first present a pulse-width self-restricted (PWSR) delay element that is capable of providing a steady delay to improve the time precision. Meanwhile, we employ the proposed PWSR delay element to construct a pair of 16-stages vernier delay-rings to effectively enlarge the dynamic range. Moreover, we propose a compact and fast arbiter using a fully symmetric topology to enhance the robustness of the TDC. To validate the performance of the proposed TDC, a prototype 13-bit TDC has been fabricated in the standard 0.18-µm complementary metal–oxide–semiconductor (CMOS) process. The core area is about 200 µm × 180 µm and the total power consumption is nearly 1.6 mW. The proposed TDC achieves a dynamic range of 92.1 ns and a time precision of 11.25 ps. The measured worst integral nonlinearity (INL) and differential nonlinearity (DNL) are respectively 0.65 least-significant-bit (LSB) and 0.38 LSB, and both of them are less than 1 LSB. The experimental results indicate that the proposed TDC is suitable for SPAD-based 3D imaging applications.

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