Monolayer Nitrogen-Atom Distributions in Ultrathin Gate Dielectrics by Low-Temperature Low-Thermal-Budget Processing

1995 ◽  
Vol 34 (Part 1, No. 12B) ◽  
pp. 6827-6837 ◽  
Author(s):  
Gerald Lucovsky ◽  
David R. Lee ◽  
Sunil V. Hattangady ◽  
Hiro Niimi ◽  
Ze Jing ◽  
...  
1996 ◽  
Vol 446 ◽  
Author(s):  
G. Lucovsky

AbstractThe research in this paper is based on an approach to low‐temperature/low‐thermal budget device fabrication that combines plasma and rapid thermal processing, and which has been customized to control separately: (i) the N‐atom bonding chemistry and composition profiles, and (ii) the structural and chemical relaxations necessary for device‐quality performance and reliability for stacked gate structures. Control of N‐atom incorporation at the monolayer level at the crystalline‐Si and polycrystalline‐Si interfaces of field effect transistors, and at alloy levels within the bulk dielectrics has been achieved by combining low‐temperature (∼300°C) plasma‐assisted processes to generate the N‐atom concentration profiles, with low‐thermal‐budget rapid thermal annealing (RTA) to promote chemical and structural relaxations that minimize defects and defect precursors.


1996 ◽  
Vol 17 (11) ◽  
pp. 503-505 ◽  
Author(s):  
Hsiao-Yi Lin ◽  
Chun-Yen Chang ◽  
Tan Fu Lei ◽  
Feng-Ming Liu ◽  
Wen-Luh Yang ◽  
...  

1999 ◽  
Vol 567 ◽  
Author(s):  
S. C. Song ◽  
C. H. Lee ◽  
H. F. Luan ◽  
D. L. Kwong ◽  
M. Gardner ◽  
...  

ABSTRACTIn this paper, we report a novel low thermal budget process (<800°C) for engineered ultra thin oxynitride dielectrics with high nitrogen concentration (>5% a.c.) using vertical high pressure (VHP) process. VHP grown oxynitride films show >1 OX lower leakage current, higher drive current and superior hot-carrier reliability compared to control SiO2 of identical thickness (Tox,eq) grown by RTP in O2.


1992 ◽  
Vol 258 ◽  
Author(s):  
Lynnita Knoch ◽  
Gordon Tam ◽  
N. David Theodore ◽  
Ron Pennell

ABSTRACTFabrication of SiGe heterojunction bipolar transistors (HBTs) requires a low thermal budget to avoid relaxation of the strained SiGe base layer. Ion implantation is one of the most widely used techniques to achieve contacts. However, due to thermal budget constraints, low temperature rapid thermal annealing (RTA) cycles to activate these implants are insufficient to anneal out all of the implant damage. Polysilicon contacts provide an alternative to ion implantation, but are typically annealed at high temperatures (>950°C) to achieve low sheet resistivity. In this study, amorphous silicon and polycrystalline silicon films were implanted with boron, arsenic, or phosphorus and RTA'd at temperatures from 800°C to 950°C and compared to single crystal silicon with identical implants and RTA cycles. The films were characterized using four-point probe, Hall measurements, TEM (transmission electron microscopy), and SIMS (secondary-ion mass-spectrometry). TEM analysis shows that the amorphous deposition produces larger grains upon RTA due to more rapid grain growth than the polycrystalline deposition. The sheet resistance for the amorphous deposited films is much lower than that of the polycrystalline deposition for all implant conditions. Activations of the implants indicate that the arsenic and phosphorus segregate to the grain boundaries, while the boron does not. The segregation is more significant for the polycrystalline films than for the amorphous films and can be explained by the grain boundary area. For contacts to the SiGe HBT, which requires a low thermal budget, an amorphous deposited silicon film is advantageous over a polycrystalline film at low annealing temperatures because it has lower sheet resistance, less segregation to the grain boundaries, and produces larger grains.


1997 ◽  
Vol 470 ◽  
Author(s):  
G. Lucovsky ◽  
B. Hinds

ABSTRACTDevice quality gate dielectric heterostructures have been prepared using a three step plasma/rapid thermal sequence [1] in which kinetic effects determine the time-temperature aspects of the processing. The steps for forming the interface and for depositing dielectric layers have been performed at low temperature, ∼300°C, by plasma-assisted processing. Following this a low rapid thermal anneal (RTA) provides interface and bulk dielectric chemical and structural relaxations, thereby yielding device performance and reliability essentially the same as obtained using higher thermal budget conventional or rapid thermal processing.


2010 ◽  
Vol 16 (1) ◽  
pp. 106-113 ◽  
Author(s):  
Kah-Wee Ang ◽  
Tsung-Yang Liow ◽  
Ming-Bin Yu ◽  
Qing Fang ◽  
Junfeng Song ◽  
...  

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