Device Performance Improvement Based on Transient Enhanced Diffusion Suppression in the Deep Sub-Quarter Micron Scale

2000 ◽  
Vol 39 (Part 1, No. 4B) ◽  
pp. 2172-2176
Author(s):  
Hyun-Sik Kim ◽  
Jong-Hyon Ahn ◽  
Duk-Min Lee ◽  
Kwang-Dong Yoo ◽  
Soo-Cheol Lee ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Device Performance ◽  
Enhanced Diffusion ◽  
Transient Enhanced Diffusion

A Novel High-Stress Pre-Metal Dielectric Film to Improve Device Performance for sub-65nm CMOS Manufacturing

2006 ◽  
Vol 913 ◽  
Author(s):  
Young Way Teh ◽  
John Sudijono ◽  
Alok Jain ◽  
Shankar Venkataraman ◽  
Sunder Thirupapuliyur ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Dielectric Film ◽  
High Stress ◽  
Significant Degree ◽  
Strain Effect ◽  
Device Performance ◽  
Hot Carrier ◽  
Tcad Simulation ◽  
Improve Device ◽  
Deposition Techniques

AbstractThis work focuses on the development and physical characteristics of a novel dielectric film for a pre-metal dielectric (PMD) application which induces a significant degree of tensile stress in the channel of a sub-65nm node CMOS structure. The film can be deposited at low temperatures to meet the requirements of NiSi integration while maintaining void-free gap fill and superior film quality such as moisture content and uniformity. A manufacturable and highly reliable oxide film has been demonstrated through both TCAD simulation and real device data, showing ~6% NMOS Ion-Ioff improvement; no Ion-Ioff improvement or degradation on PMOS. A new concept has been proposed to explain the PMD strain effect on device performance improvement. Improvement in Hot Carrier immunity is observed compared to similar existing technologies using high density plasma (HDP) deposition techniques.

scholarly journals Enhanced Diffusion of Dopants in Vacancy Supersaturation Produced by MeV Implantation

1997 ◽  
Vol 469 ◽  
Author(s):  
V. C. Venezia ◽  
T. E. Haynes ◽  
A. Agarwal ◽  
H. -J. Gossmann ◽  
D. J. Eaglesham
Keyword(s):  
Surface Layer ◽  
Surface Region ◽  
Silicon On Insulator ◽  
Rich Region ◽  
Near Surface ◽  
Enhanced Diffusion ◽  
Float Zone ◽  
Transient Enhanced Diffusion

ABSTRACTThe diffusion of Sb and B markers has been studied in vacancy supersaturations produced by MeV Si implantation in float zone (FZ) silicon and bonded etch-back silicon-on-insulator (BESOI) substrates. MeV Si implantation produces a vacancy supersaturated near-surface region and an interstitial-rich region at the projected ion range. Transient enhanced diffusion (TED) of Sb in the near surface layer was observed as a result of a 2 MeV Si+, 1×1016/cm2, implant. A 4× larger TED of Sb was observed in BESOI than in FZ silicon, demonstrating that the vacancy supersaturation persists longer in BESOI than in FZ. B markers in samples with MeV Si implant showed a factor of 10× smaller diffusion relative to markers without the MeV Si+ implant. This data demonstrates that a 2 MeV Si+ implant injects vacancies into the near surface region.

Ultra Shallow Junction Formation by B+/BF2+ Implantation at Energy of 0.5 KEV

1998 ◽  
Vol 532 ◽  
Author(s):  
M. Kase ◽  
Y Kikuchi ◽  
H. Niwa ◽  
T. Kimura
Keyword(s):  
Junction Depth ◽  
Shallow Junction ◽  
Enhanced Diffusion ◽  
Transient Enhanced Diffusion ◽  
Junction Formation

ABSTRACTThis paper describes ultra shallow junction formation using 0.5 keV B+/BF2+ implantation, which has the advantage of a reduced channeling tail and no transient enhanced diffusion. In the case of l × 1014 cm−2, 0.5 keV BF2 implantation a junction depth of 19 nm is achieved after RTA at 950°C.

Effects of Carbon Co-Implantation on Transient Enhanced Diffusion and Performances of the Phosphorus Doped Ultra-Shallow Junction Nano NMOSFET

2013 ◽  
Vol 284-287 ◽  
pp. 98-102
Author(s):  
Hung Yu Chiu ◽  
Yean Kuen Fang ◽  
Feng Renn Juang
Keyword(s):  
Cmos Technology ◽  
Shallow Junction ◽  
Enhanced Diffusion ◽  
Transient Enhanced Diffusion ◽  
Technology Applications ◽  
Implantation Process ◽  
Phosphorus Doped

The carbon (C) co-implantation and advanced flash anneal were employed to form the ultra shallow junction (USJ) for future nano CMOS technology applications. The effects of the C co-implantation process on dopant transient enhanced diffusion (TED) of the phosphorus (P) doped nano USJ NMOSFETs were investigated in details. The USJ NMOSFETs were prepared by a foundry’s 55 nano CMOS technology. Various implantation energies and doses for both C and P ions were employed. Results show the suppression of the TED is strongly dependent on both C and P implantation conditions. Besides, the mechanisms of P TED and suppression by C ion co-implantation were illustrated comprehensively with schematic models.

High Performance 0.2 µm Dual Gate Complementary MOS Technologies by Suppression of Transient-Enhanced-Diffusion using Rapid Thermal Annealing

1998 ◽  
Vol 37 (Part 1, No. 3B) ◽  
pp. 1054-1058 ◽  
Author(s):  
Yukio Nishida ◽  
Hirokazu Sayama ◽  
Satoshi Shimizu ◽  
Takashi Kuroi ◽  
Akihiko Furukawa ◽  
...  
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
High Performance ◽  
Enhanced Diffusion ◽  
Transient Enhanced Diffusion ◽  
Dual Gate

Performance Improvement of Trench-Gate SiC MOSFETs by Localized High-Concentration N-Type Ion Implantation

2020 ◽  
Vol 1004 ◽  
pp. 770-775
Author(s):  
Rina Tanaka ◽  
Katsutoshi Sugawara ◽  
Yutaka Fukui ◽  
Hideyuki Hatta ◽  
Hidenori Koketsu ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Short Circuit ◽  
Effective Means ◽  
Gate Oxide ◽  
Device Performance ◽  
High Concentration ◽  
Safe Operation ◽  
Major Drawback ◽  
Oxide Reliability ◽  
Conventional Device

Gate oxide reliability of a trench-gate SiC MOSFET can be improved by incorporating a gate protection structure, but the resulting parasitic JFET resistance is one major drawback. For reduction of on-resistance, a new method of localized high-concentration n-type doping in JFET regions (JD) is developed. Utilizing process and device simulation by TCAD, the optimal condition of JD that enables maximum device performance is derived. By fabricating a device with the optimal JD structure, the on-resistance is successfully reduced by 25% compared to a conventional device without JD, while maintaining the withstand voltage and the gate oxide electric field at the same level. As a result, a device exhibiting a specific on-resistance of 1.84 mΩcm2 and a breakdown voltage of 1560 V is obtained. The optimal JD structure maintains the short-circuit safe operation area comparable to that for the structure without JD. Thus, by reducing the JFET resistance while minimizing effects on other characteristics, localized JD is shown to be an effective means of realizing a reliable, low-resistance SiC power device.

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