Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages

We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS) techniques for power optimizations. We introduce a fast heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the load capacitance of the gates. Our results show that the combination of VS and GS perform better than the techniques applied in isolation. An average power reduction of 73% is obtained when decisions are taken assuming dynamic power only. In contrast, average power reduction is 77% when decisons include the short circuit power dissipation.

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A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.2764 ◽

2017 ◽

Vol E100.A (12) ◽

pp. 2764-2775 ◽

Cited By ~ 1

Author(s):

Jun SHIOMI ◽

Tohru ISHIHARA ◽

Hidetoshi ONODERA

Keyword(s):

Minimum Energy ◽

Cmos Circuits ◽

Sufficient Condition ◽

Necessary And Sufficient Condition ◽

Energy Point ◽

Threshold Voltages ◽

Necessary And Sufficient ◽

Minimum Energy Point

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A 0.6-V to 1-V Audio ΔΣ Modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V

VLSI Design ◽

10.1155/2013/353080 ◽

2013 ◽

Vol 2013 ◽

pp. 1-9 ◽

Cited By ~ 1

Author(s):

Liyuan Liu ◽

Dongmei Li ◽

Zhihua Wang

Keyword(s):

Power Dissipation ◽

Total Power ◽

Third Order ◽

Power Cost ◽

Threshold Voltages ◽

Nonlinear Amplifier ◽

Amplifier Gain ◽

Low Threshold ◽

Single Comparator ◽

Circuit Techniques

This paper presents a discrete time, single loop, third order ΔΣ modulator. The input feed forward technique combined with 5-bit quantizer is adopted to suppress swings of integrators. Harmonic distortions as well as the noise mixture due to the nonlinear amplifier gain are prevented. The design of amplifiers is hence relaxed. To reduce the area and power cost of the 5-bit quantizer, the successive approximation quantizer with only a single comparator instead of traditional flash quantizer is employed. Fabricated in 65 nm CMOS, the modulator achieves 95 dB peak SNDR at 1-V supply with 24 kHz. Thanks to low swing circuit techniques and low threshold voltages of devices, the peak SNDR maintains 90.2 dB under 0.6-V low supply. The total power dissipation is 371 μW at 1-V and drops to only 133 μW at 0.6-V.

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