scholarly journals A 0.6-V to 1-V Audio ΔΣ Modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Liyuan Liu ◽  
Dongmei Li ◽  
Zhihua Wang
Keyword(s):  
Power Dissipation ◽  
Total Power ◽  
Third Order ◽  
Power Cost ◽  
Threshold Voltages ◽  
Nonlinear Amplifier ◽  
Amplifier Gain ◽  
Low Threshold ◽  
Single Comparator ◽  
Circuit Techniques

This paper presents a discrete time, single loop, third order ΔΣ modulator. The input feed forward technique combined with 5-bit quantizer is adopted to suppress swings of integrators. Harmonic distortions as well as the noise mixture due to the nonlinear amplifier gain are prevented. The design of amplifiers is hence relaxed. To reduce the area and power cost of the 5-bit quantizer, the successive approximation quantizer with only a single comparator instead of traditional flash quantizer is employed. Fabricated in 65 nm CMOS, the modulator achieves 95 dB peak SNDR at 1-V supply with 24 kHz. Thanks to low swing circuit techniques and low threshold voltages of devices, the peak SNDR maintains 90.2 dB under 0.6-V low supply. The total power dissipation is 371 μW at 1-V and drops to only 133 μW at 0.6-V.

A 1V Low Voltage 4GHz Phase-Switching Dual-Modulus Prescaler in 0.18μm CMOS

2013 ◽  
Vol 364 ◽  
pp. 444-448
Author(s):  
Liang Yuan ◽  
Xiang Ning Fan
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Driving Ability ◽  
Phase Switching ◽  
Voltage Phase ◽  
Low Threshold ◽  
Simulation Results ◽  
Circuit Techniques

A 1V low-voltage phase switching dual-modulus prescaler in standard 0.18μm TSMC RF CMOS technology is presented. Forward phase switching technique is used to prevent glitches. Low threshold voltage transistors are applied to overcome low voltage supply. Circuit techniques are used to improve driving ability and ensure reliability. The post simulation results show the prescaler operates correctly from 0.8GHz to 4GHz with power dissipation of 2.059mW at a maximum input frequency of 4GHz from 1V power supply.

PERFORMANCE ANALYSIS OF FULL ADDERS IN CIC DECIMATION FILTER

2019 ◽  
Vol 7 (SI-TeMIC18) ◽  
Author(s):  
Yeoh Poay Zheng ◽  
Lini Lee
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Full Adder ◽  
Total Power ◽  
Huge Amount ◽  
Third Order ◽  
Delta Sigma ◽  
Cic Filter ◽  
Decimation Filter ◽  
Power Delay Product

This article presents analysis of various full adder architecture on Cascaded Integrator-Comb (CIC) filter of delta-sigma ADC. The structure of CIC filter consists of an integrator and a differentiator stage that is built from a cascaded full adder and delay element. Since each of the element within CIC filter has its own low-power architecture, full adder is one of the block that consumes huge amount of power compared to others. In this paper, four different type of full adder’s architecture is designed and simulated with CIC decimation filter. There are 28T conventional, pseudo-NMOS adder, 16T hybrid adder and modified 14T hybrid adder. The performance parameters such as delay, total power dissipation and power delay product (PDP) of CIC filter were compared. This analysis shows that 16T hybrid full adder CIC filter has reduced up to 38.15% of power consumption and 39.18% of power product delay compared to conventional adder. Hence, a complete 1-bit third order of 16T hybrid adder CIC filter is implemented with size area of 118.23µm × 22.38µm. Keywords: Delta-sigma ADC, Low-power, CIC decimation filter, Full adder

scholarly journals Nonvolatile Ternary Resistive Memory Performance of a Benzothiadiazole-Based Donor–Acceptor Material on ITO-Coated Glass

Coatings ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 318
Author(s):  
Yang Li ◽  
Cheng Zhang ◽  
Zhiming Shi ◽  
Jingni Li ◽  
Qingyun Qian ◽  
...  
Keyword(s):  
Data Storage ◽  
High Performance ◽  
Memory Performance ◽  
Resistive Memory ◽  
Molecular Systems ◽  
Threshold Voltages ◽  
Donor Acceptor ◽  
Low Threshold ◽  
Multilevel Memory ◽  
Further Development

The explosive growth of data and information has increasingly motivated scientific and technological endeavors toward ultra-high-density data storage (UHDDS) applications. Herein, a donor−acceptor (D–A) type small conjugated molecule containing benzothiadiazole (BT) is prepared (NIBTCN), which demonstrates multilevel resistive memory behavior and holds considerable promise for implementing the target of UHDDS. The as-prepared device presents distinct current ratios of 105.2/103.2/1, low threshold voltages of −1.90 V and −3.85 V, and satisfactory reproducibility beyond 60%, which suggests reliable device performance. This work represents a favorable step toward further development of highly-efficient D−A molecular systems, which opens more opportunities for achieving high performance multilevel memory materials and devices.

LOW-LEAKAGE FLIP-FLOPS BASED ON DUAL-THRESHOLD AND MULTIPLE LEAKAGE REDUCTION TECHNIQUES

2011 ◽  
Vol 20 (01) ◽  
pp. 147-162 ◽  
Author(s):  
WEIQIANG ZHANG ◽  
LI SU ◽  
YU ZHANG ◽  
LINFENG LI ◽  
JIANPING HU
Keyword(s):  
Total Power ◽  
High Threshold ◽  
Leakage Currents ◽  
Flip Flop ◽  
Leakage Reduction ◽  
Low Leakage ◽  
Reduction Techniques ◽  
Low Threshold ◽  
Critical Paths ◽  
P Type

The scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS and multiple leakage reduction techniques to reduce their leakage dissipations. In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors on non-critical paths use high-threshold devices to reduce their leakage currents, while the other transistors on critical paths use low-threshold devices to maintain performance. The MLRT FF (Multiple Leakage Reduction Technique Flip-Flop) uses P-type CMOS techniques, MTCMOS (Multi-Threshold CMOS) power-gating and dual-threshold technique to reduce both sub-threshold and gate leakage dissipations. Taken as an example, a practical sequential system realized with the two low-leakage flip-flops is demonstrated using a mode-5 × 5 × 5 counter. The simulation results show that the two flip-flops achieve considerable leakage reductions.

Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop

2014 ◽  
Vol 573 ◽  
pp. 187-193 ◽  
Author(s):  
Anitha Ponnusamy ◽  
Palaniappan Ramanathan
Keyword(s):  
Integrated Circuit ◽  
Power Dissipation ◽  
High Speed ◽  
Total Power ◽  
Single Chip ◽  
Flip Flop ◽  
Design And Optimization ◽  
Negative Edge ◽  
Carry Select Adder ◽  
Power Delay Product

The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. The results reveal that for 16 bit CSA improvement of power delay product (PDP) of the proposed design using negative edge triggered D flip flop is 78% & 18% when compared to CSA with BEC and CSA with conventional D flip flop. When CSA implemented in a partitioned Dadda multiplier it results in performance improvement of 74 % with little increase in total power dissipation.

Thermal Performance Evaluation and Economic Analysis of LED Integrated with Thermoelectric Cooler Package

2011 ◽  
Vol 216 ◽  
pp. 106-110 ◽  
Author(s):  
Hong Qin ◽  
Da Liang Zhong ◽  
Chang Hong Wang
Keyword(s):  
Economic Analysis ◽  
Thermal Performance ◽  
Power Dissipation ◽  
Heat Dissipation ◽  
Light Emitting Diode ◽  
Vital Role ◽  
Junction Temperature ◽  
Total Power ◽  
Thermoelectric Cooler ◽  
Light Emitting

Thermal management is an important issue for light emitting diodes’ utilization. For high power light emitting diode (LED), active heat dissipation method plays a vital role. As a new cooling device, thermoelectric cooler (TEC) is applied in LED packaging for the precisely temperature controlled advantage. In order to evaluate the thermal performance of the TEC packaging designs in LED, experimental measurement is used to assess the chip’s junction temperature of three different cooling models, which include the heatsink model, the heatsink and fan model and the TEC, heatsink and fan model. Based on the research, it is better to apply TEC cooling methods with the power dissipation of LED less than 35 W and the wind speed is 3.6 m/s. However, the power dissipation of TEC itself plays a vital role of the total power dissipation of LED packaging. The results of economic analysis shows that the LED integrated with TEC package achieves 22.34% and 44.73% electric energy saving under the condition of 20 W and 30 W power dissipation of the LED chip contrasts to the fluorescent lamp, but sacrifices 2.71% electric power under the condition of 10 W power dissipation of the LED chip.

An Improved CAL Register File with Dual-Threshold Technique for Leakage Reduction

2010 ◽  
Vol 159 ◽  
pp. 186-191 ◽  
Author(s):  
Jian Ping Hu ◽  
Jia Guo Zhu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Total Power ◽  
Cmos Process ◽  
Register File ◽  
Mos Transistors ◽  
Leakage Currents ◽  
Micro Power ◽  
Scaling Down ◽  
Threshold Technique

Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. The leakage dissipation caused by leakage currents is becoming an increasingly important fraction of the total power dissipation in nanometer integrated circuits. To decrease leakage power dissipations is becoming more and more important in micro-power nanometer circuits. An improved CAL register file using DTCMOS (Dual-Threshold Technique) for reducing leakage dissipations in active mode is addressed in this paper. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE at 45nm CMOS process. Simulation results show that the register file with dual-threshold can reduce about 15.6% power dissipations.

scholarly journals Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 27-30
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Power Analysis ◽  
Research Work ◽  
Leakage Power ◽  
Total Power ◽  
Voltage Supply ◽  
Field Programmable ◽  
Eda Tools

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

scholarly journals Accuracy and Physical Characterization of Approximate Arithmetic Circuits

2020 ◽  
Author(s):  
Daniela Catelan ◽  
Ricardo Santos ◽  
Liana Duenha
Keyword(s):  
Power Dissipation ◽  
Power Efficiency ◽  
Arithmetic Circuits ◽  
Approximate Computing ◽  
Accuracy Control ◽  
Field Programmable ◽  
Speed Up ◽  
Circuit Techniques ◽  
The Cost

With the end of Dennard's scale, designers have been looking for new alternatives and approximate computing (AC) has managed to attract the attention of researchers, by offering techniques ranging from the application level to the circuit level. When applying approximate circuit techniques in hardware design, the program user may speed up the application while a designer may save area and power dissipation at the cost of less accuracy on the operations results. This paper discusses the compromise between accuracy versus physical efficiency by presenting a set of experiments and results of tailor-made approximate arithmetic circuits on Field-Programmable Gate Array (FPGA) platforms. Our results reveal that an approximate circuit with accuracy control could not be useful if the goal is to save circuit area or even power dissipation. Even for circuits that seem to have power efficiency, we should care about the size and prototyping platform where the hardware will be used.

System Level Thermal Optimization of an Automotive Lightning Module Incorporating Several Power Devices

2007 ◽  
Author(s):  
Victor Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Performance ◽  
Power Dissipation ◽  
Heat Dissipation ◽  
System Level ◽  
Total Power ◽  
Main Concern ◽  
Optimized Design ◽  
Passive Components ◽  
Thermal Budget ◽  
The Impact

The conjugate thermal performance of microelectronics module incorporating several power packages and additional passive components in a custom environment is evaluated and further optimized using numerical simulation and experimental validation. The automotive industry deals on a daily basis with multiple packaging and module-level thermal issues when reducing the size of components for a lightning system in a car, while managing the routing of very high current. The study provides a better understanding of the strengths and weaknesses of the IC incorporation into a system module level, for both present and future product development. The reference design is evaluated at a system level, and several improvements are identified to enhance the overall thermal performance of the lightning system. The main concern is related to the possibility of exceeding the thermal budget for a large system incorporating several PQFN (Power Quad Flat No-Lead Package) packages with additional heat dissipation devices in an enclosure, at an external ambient temperature of 85°C. Due to the compactness of the device, there are only limited solutions to extract the heat from the high power dissipation system. The impact on the thermal balance of the trace dissipation, the location and size of the pins connecting the two boards (motherboard and daughter board) forming the system, the header heating and other passive components under various powered conditions are evaluated. A revised model includes additional pins (reduced diameter), modified motherboard and harness structures and their locations; the impact of additional heater traces on both top and bottom surfaces of the motherboard, and a modified daughter board design, is also evaluated. The resulting peak temperatures range from 118.3°C to 137.3°C and the corresponding junction-to-ambient thermal resistances (Rja) vary from 8.4°C/W to 8.8°C/W. Rja is defined as the temperature difference between the peak device and ambient divided by the total power dissipation of the PQFN packages. An optimized design is further evaluated, with lowered thermal resistance from the motherboard, the board-to-board pins, the junction box board, and the wiring harness. The thermal budget is satisfied, as the peak temperatures reached by the two designs are below the 150°C limit. Additional experimental results are used to benchmark the simulation results, within 1–6% accuracy.

Sign in / Sign up

Export Citation Format

Share Document