TAMA

Nowadays, static power consumption in chip multiprocessor (CMP) is the most crucial concern of chip designers. Power-gating is an effective approach to mitigate static power consumption particularly in low utilization. Network-on-Chip (NoC) as the backbone of multi- and many-core chips has no exception. Previous state-of-the-art techniques in power-gating desire to decrease static power consumption alongside the lack of diminution in performance of NoC. However, maintaining the performance and utilization of the power-gating approach has not yet been addressed very well. In this article, we propose TAMA (Turn-Aware Mapping & Architecture) as an effective method to boost the performance of the TooT method that was only powering on a router during turning pass or packet injection. In other words, in the TooT method, straight and eject packets pass the router via a bypass route without powering on the router. By employing meta-heuristic approaches (Genetic and Ant Colony algorithms), we develop a specific application mapping that attempts to decrease the number of turns through interconnection networks. Accordingly, the average latency of packet transmission decreases due to fewer turns. Also, by powering on turn routers in advance with lightweight hardware, the latency of sending packets diminishes. The experimental results demonstrate that our proposed approach, i.e., TAMA achieves more than 13% reduction in packet latency of NoC in comparison with TooT. Besides the packet latency, the power consumption of TAMA is reduced by about 87% compared to the traditional approach.

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Efficient Instruction and Data Caching for High Performance Embedded Processors

Jornada de Jóvenes Investigadores del I3A ◽

10.26754/jji-i3a.201201788 ◽

1970 ◽

pp. 9

Author(s):

A. Ferrerón Labari ◽

D. Suárez Gracia ◽

V. Viñals Yúfera

Keyword(s):

Embedded Systems ◽

Power Consumption ◽

Low Power ◽

Interconnection Networks ◽

High Performance ◽

Critical Issue ◽

Content Management ◽

Structure Design ◽

Portable Devices ◽

On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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Design for Test and Diagnosis of Power Switches

Journal of Circuits System and Computers ◽

10.1142/s0218126616400132 ◽

2015 ◽

Vol 25 (03) ◽

pp. 1640013

Author(s):

Miroslav Valka ◽

Alberto Bosio ◽

Luigi Dilillo ◽

Patrick Girard ◽

Arnaud Virazel ◽

...

Keyword(s):

Power Consumption ◽

Industrial Test ◽

Design For Test ◽

Power Gating ◽

Test Quality ◽

Worst Case ◽

Manufacturing Defects ◽

Efficient Test ◽

Power Switches ◽

Static Power

Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affecting PSs can lead to increase in the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and diagnosis solutions are needed. In this paper, we present a novel Design for Test and Diagnosis (DfTD) solution able to increase the test quality and diagnosis accuracy of PSs. The proposed approach has been validated through SPICE simulations on ITC’99 benchmark circuits as well as on industrial test cases.

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A Novel Approach to Reduce Packet Latency Increase Caused by Power Gating in Network-on-Chip

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip - NOCS '17 ◽

10.1145/3130218.3130220 ◽

2017 ◽

Cited By ~ 5

Author(s):

Peng Wang ◽

Sobhan Niknam ◽

Zhiying Wang ◽

Todor Stefanov

Keyword(s):

Network On Chip ◽

Power Gating ◽

Novel Approach ◽

Packet Latency ◽

On Chip

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Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

Journal of Electrical and Computer Engineering ◽

10.1155/2015/862387 ◽

2015 ◽

Vol 2015 ◽

pp. 1-16 ◽

Cited By ~ 1

Author(s):

Feng Wang ◽

Xiantuo Tang ◽

Zuocheng Xing

Keyword(s):

Power Efficiency ◽

Network Performance ◽

Routing Algorithm ◽

Network On Chip ◽

Leakage Power ◽

Power Gating ◽

Load Range ◽

Communication Architectures ◽

On Chip ◽

Many Core

Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.

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A Multi-Phase Based Multi-Application Mapping Approach for Many-Core Networks-on-Chip

Micromachines ◽

10.3390/mi12060613 ◽

2021 ◽

Vol 12 (6) ◽

pp. 613

Author(s):

Fen Ge ◽

Chenchen Cui ◽

Fang Zhou ◽

Ning Wu

Keyword(s):

Simulated Annealing Algorithm ◽

Optimal Placement ◽

Networks On Chip ◽

Core Networks ◽

Application Mapping ◽

Mapping Approach ◽

On Chip ◽

The One ◽

Multi Phase ◽

Many Core

More and more attention is being paid to the use of massive parallel computing performed on many-core Networks-on-Chip (NoC) in order to accelerate performance. Simultaneously deploying multiple applications on NoC is one feasible way to achieve this. In this paper, we propose a multi-phase-based multi-application mapping approach for NoC design. Our approach began with a rectangle analysis, which offered several potential regions for application. Then we mapped all tasks of the application into these potential regions using a genetic algorithm, and identified the one which exhibited the strongest performance. When the packeted regions for each application were identified, a B*Tree-based simulated annealing algorithm was used to generate the optimal placement for the multi-application mapping regions. The experiment results show that the proposed approach can achieve a considerable reduction in network power consumption (up to 23.45%) and latency (up to 24.42%) for a given set of applications.

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Design and Implementation of an On-Chip Low-Power and High-Flexibility System for Data Acquisition and Processing of an Inertial Measurement Unit

Sensors ◽

10.3390/s20020462 ◽

2020 ◽

Vol 20 (2) ◽

pp. 462 ◽

Cited By ~ 1

Author(s):

Zhenyi Gao ◽

Bin Zhou ◽

Yang Li ◽

Lei Yang ◽

Xiang Li ◽

...

Keyword(s):

Signal Processing ◽

Power Consumption ◽

Low Power ◽

Inertial Measurement Unit ◽

Measurement Unit ◽

Low Power Consumption ◽

Inertial Measurement ◽

Static Power ◽

On Chip ◽

Application Specific

For signal processing of a Micro-Electro-Mechanical System (MEMS) Inertial Measurement Unit (IMU), a digital-analog hybrid system-on-chip (SoC) with small area and low power consumption was designed and implemented in this paper. To increase the flexibility of the processing circuit, the designed SoC integrates a low-power processor and supports three startup or debugging modes for different application scenarios. An application-specific computing module and communication interface are designed in the circuit to meet the requirements of IMU signal processing. The configurable clock allows users to dynamically balance computing speed and power consumption in their applications. The chip was taped out under SMIC 180 nm CMOS technology and tested for performance. The results show that the chip’s maximum running frequency is 105 MHz. The total area is 33.94 mm 2 . The dynamic and static power consumption are 0.65 mW/MHz and 0.30 mW/MHz, respectively. When the system clock is 25 MHz, the dynamic and static power consumption of the chip is 76 mW and 66 mW, and the dynamic and static power consumption of the FPGA level are 634 mW and 520 mW. The results verify the superiority of the application specific integrated circuit (ASIC) solution in terms of integration and low power consumption.

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Hybrid Network-on-Chip: An Application-Aware Framework for Big Data

Complexity ◽

10.1155/2018/1040869 ◽

2018 ◽

Vol 2018 ◽

pp. 1-11

Author(s):

Juan Fang ◽

Sitong Liu ◽

Shijian Liu ◽

Yanjin Cheng ◽

Lu Yu

Keyword(s):

Energy Efficiency ◽

Big Data ◽

Power Consumption ◽

High Performance ◽

Network On Chip ◽

Hybrid Network ◽

Big Data Applications ◽

Application Aware ◽

On Chip ◽

Many Core

Burst growing IoT and cloud computing demand exascale computing systems with high performance and low power consumption to process massive amounts of data. Modern system platforms based on fundamental requirements encounter a performance gap in chasing exponential growth in data speed and amount. To narrow the gap, a heterogamous design gives us a hint. A network-on-chip (NoC) introduces a packet-switched fabric for on-chip communication and becomes the de facto many-core interconnection mechanism; it refers to a vital shared resource for multifarious applications which will notably affect system energy efficiency. Among all the challenges in NoC, unaware application behaviors bring about considerable congestion, which wastes huge amounts of bandwidth and power consumption on the chip. In this paper, we propose a hybrid NoC framework, combining buffered and bufferless NoCs, to make the NoC framework aware of applications’ performance demands. An optimized congestion control scheme is also devised to satisfy the requirement in energy efficiency and the fairness of big data applications. We use a trace-driven simulator to model big data applications. Compared with the classical buffered NoC, the proposed hybrid NoC is able to significantly improve the performance of mixed applications by 17% on average and 24% at the most, decrease the power consumption by 38%, and improve the fairness by 13.3%.

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Intelligent On/Off Dynamic Link Management for On-Chip Networks

Journal of Electrical and Computer Engineering ◽

10.1155/2012/107821 ◽

2012 ◽

Vol 2012 ◽

pp. 1-12 ◽

Cited By ~ 2

Author(s):

Andreas G. Savva ◽

Theocharis Theocharides ◽

Vassos Soteriou

Keyword(s):

Power Consumption ◽

Past Research ◽

System Level ◽

Management Policy ◽

Dynamic Power Management ◽

Threshold Mechanism ◽

Level Information ◽

Static Power ◽

Network Topologies ◽

On Chip

Networks-on-chips (NoCs) provide scalable on-chip communication and are expected to be the dominant interconnection architectures in multicore and manycore systems. Power consumption, however, is a major limitation in NoCs today, and researchers have been constantly working on reducing both dynamic and static power. Among the NoC components, links that connect the NoC routers are the most power-hungry components. Several attempts have been made to reduce the link power consumption at both the circuit level and the system level. Most past research efforts have proposed selective on/off link state switching based on system-level information based on link utilization levels. Most of these proposed algorithms focus on a pessimistic and simple static threshold mechanism which determines whether or not a link should be turned on/off. This paper presents an intelligent dynamic power management policy for NoCs with improved predictive abilities based on supervised online learning of the system status (i.e., expected future utilization link levels), where links are turned off and on via the use of a small and scalable neural network. Simulation results with various synthetic traffic models over various network topologies show that the proposed work can reach up to 13% power savings when compared to a trivial threshold computation, at very low (<4%) hardware overheads.

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Leakage Power Reduction in 32-bit Digital Comparator Using Modified Power Gating Technique

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.742.741 ◽

2015 ◽

Vol 742 ◽

pp. 741-744 ◽

Cited By ~ 1

Author(s):

G. Amuthavalli ◽

R. Gunasundari ◽

A. Nijandan

Keyword(s):

Power Consumption ◽

High Performance ◽

Channel Length ◽

Power Reduction ◽

Leakage Power ◽

Power Gating ◽

Dynamic Power ◽

Digital Comparator ◽

Static Power ◽

Scaling Down

As scaling down of CMOS transistor’s channel length is done for miniaturization, the design community primarily focuses on the high performance & power-aware design. The power consumption of any circuit solely holds the performance and the life of it. But static power consumption deteriorates them and dominates the dynamic power consumption because of its leakage components. A modified approach of pulse triggering in the Power Gating technique called MPG (Modified Power Gating) is proposed to reduce the static power consumption (leakage power) of digital subsystems. Sub threshold leakage power of MPG Inverter (INV) and 32-bit Digital Comparator (DC) is analyzed and reduced with 35% to 40% leakage savings compared with conventional and existing techniques by simulating it in Cadence GPDK.

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