scholarly journals Large-scale recording of thalamocortical circuits: in vivo electrophysiology with the two-dimensional electronic depth control silicon probe

2016 ◽  
Vol 116 (5) ◽  
pp. 2312-2330 ◽  
Author(s):  
Richárd Fiáth ◽  
Patrícia Beregszászi ◽  
Domonkos Horváth ◽  
Lucia Wittner ◽  
Arno A. A. Aarts ◽  
...  
Keyword(s):  
Large Scale ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Electrophysiological Recording ◽  
Multielectrode Arrays ◽  
Two Dimensional ◽  
Single Experiment ◽  
Brain Functions ◽  
Depth Control

Recording simultaneous activity of a large number of neurons in distributed neuronal networks is crucial to understand higher order brain functions. We demonstrate the in vivo performance of a recently developed electrophysiological recording system comprising a two-dimensional, multi-shank, high-density silicon probe with integrated complementary metal-oxide semiconductor electronics. The system implements the concept of electronic depth control (EDC), which enables the electronic selection of a limited number of recording sites on each of the probe shafts. This innovative feature of the system permits simultaneous recording of local field potentials (LFP) and single- and multiple-unit activity (SUA and MUA, respectively) from multiple brain sites with high quality and without the actual physical movement of the probe. To evaluate the in vivo recording capabilities of the EDC probe, we recorded LFP, MUA, and SUA in acute experiments from cortical and thalamic brain areas of anesthetized rats and mice. The advantages of large-scale recording with the EDC probe are illustrated by investigating the spatiotemporal dynamics of pharmacologically induced thalamocortical slow-wave activity in rats and by the two-dimensional tonotopic mapping of the auditory thalamus. In mice, spatial distribution of thalamic responses to optogenetic stimulation of the neocortex was examined. Utilizing the benefits of the EDC system may result in a higher yield of useful data from a single experiment compared with traditional passive multielectrode arrays, and thus in the reduction of animals needed for a research study.

Ultrasensitive broadband photodetectors based on two-dimensional Bi2O2Te films

2021 ◽  
Author(s):  
Pin Tian ◽  
Hongbo Wu ◽  
Libin Tang ◽  
Jinzhong Xiang ◽  
Rongbin Ji ◽  
...  
Keyword(s):  
Large Scale ◽  
2D Materials ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Photocurrent Density ◽  
Short Wave ◽  
Oxide Semiconductor ◽  
Light Illumination ◽  
Two Dimensional ◽  
Weak Light

Abstract Two-dimensional (2D) materials exhibit many unique optical and electronic properties that are highly desirable for application in optoelectronics. Here, we report the study of photodetector based on 2D Bi2O2Te grown on n-Si substrate. The 2D Bi2O2Te material was transformed from sputtered Bi2Te3 ultrathin film after rapid annealing at 400 ℃ for 10 min in air atmosphere. The photodetector was capable of detecting a broad wavelength from 210 nm to 2.4 μm with excellent responsivity of up to 3x105 and 2x104 AW-1, and detectivity of 4x1015 and 2x1014 Jones at deep ultraviolet (UV) and short-wave infrared (SWIR) under weak light illumination, respectively. The effectiveness of 2D materials in weak light detection was investigated by analysis of the photocurrent density contribution. Importantly, the facile growth process with low annealing temperature would allow direct large-scale integration of the 2D Bi2O2Te materials with complementary metal-oxide–semiconductor (CMOS) technology.

scholarly journals Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations

Materials ◽  
2019 ◽  
Vol 12 (17) ◽  
pp. 2745 ◽  
Author(s):  
Luis Camuñas-Mesa ◽  
Bernabé Linares-Barranco ◽  
Teresa Serrano-Gotarredona
Keyword(s):  
Neural Networks ◽  
Learning Strategies ◽  
Large Scale ◽  
Sensory Information ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Hardware Implementations ◽  
Learning Capabilities ◽  
Promising Solution

Inspired by biology, neuromorphic systems have been trying to emulate the human brain for decades, taking advantage of its massive parallelism and sparse information coding. Recently, several large-scale hardware projects have demonstrated the outstanding capabilities of this paradigm for applications related to sensory information processing. These systems allow for the implementation of massive neural networks with millions of neurons and billions of synapses. However, the realization of learning strategies in these systems consumes an important proportion of resources in terms of area and power. The recent development of nanoscale memristors that can be integrated with Complementary Metal–Oxide–Semiconductor (CMOS) technology opens a very promising solution to emulate the behavior of biological synapses. Therefore, hybrid memristor-CMOS approaches have been proposed to implement large-scale neural networks with learning capabilities, offering a scalable and lower-cost alternative to existing CMOS systems.

scholarly journals VLSI Architectures for Image Interpolation: A Survey

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
C. John Moses ◽  
D. Selvathi ◽  
V. M. Anne Sophia
Keyword(s):  
Large Scale ◽  
Piecewise Linear ◽  
Complementary Metal Oxide Semiconductor ◽  
Image Interpolation ◽  
Hardware Architecture ◽  
Oxide Semiconductor ◽  
Weighting Coefficient ◽  
Vlsi Architectures ◽  
Different Types ◽  
Memory Buffer

Image interpolation is a method of estimating the values at unknown points using the known data points. This procedure is used in expanding and contrasting digital images. In this survey, different types of interpolation algorithm and their hardware architecture have been analyzed and compared. They are bilinear, winscale, bi-cubic, linear convolution, extended linear, piecewise linear, adaptive bilinear, first order polynomial, and edge enhanced interpolation architectures. The algorithms are implemented for different types of field programmable gate array (FPGA) and/or by different types of complementary metal oxide semiconductor (CMOS) technologies like TSMC 0.18 and TSMC 0.13. These interpolation algorithms are compared based on different types of optimization such as gate count, frequency, power, and memory buffer. The goal of this work is to analyze the different very large scale integration (VLSI) parameters like area, speed, and power of various implementations for image interpolation. From the survey followed by analysis, it is observed that the performance of hardware architecture of image interpolation can be improved by minimising number of line buffer memory and removing superfluous arithmetic elements on generating weighting coefficient.

scholarly journals A Smart Floating Gate Transistor with Two Control Gates for Active Noise Control

Micromachines ◽  
2019 ◽  
Vol 10 (11) ◽  
pp. 722
Author(s):  
Mao ◽  
Yang ◽  
Ma ◽  
Yan ◽  
Zhang
Keyword(s):  
Large Scale ◽  
Noise Control ◽  
Low Cost ◽  
Active Noise Control ◽  
Complementary Metal Oxide Semiconductor ◽  
Floating Gate ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Active Noise ◽  
Floating Gate Transistor

A smart floating gate transistor with two control gates was proposed for active noise control in bioelectrical signal measurement. The device, which is low cost and capable of large-scale integration, was implemented in a standard single-poly complementary metal–oxide–semiconductor (CMOS) process. A model of the device was developed to demonstrate the working principle. Theoretical analysis and simulation results proved the superposition of the two control gates. A series of test experiments were carried out and the results showed that the device was in accordance with the basic electrical characteristics of a floating gate transistor, including the current–voltage (I–V) characteristics and the threshold characteristics observed on the two control gates. Based on the source follower circuit, the experimental results proved that the device can reduce interference by more than 29 dB, which demonstrates the feasibility of the proposed device for active noise control.

scholarly journals High-speed programmable photonic circuits in a cryogenically compatible, visible–near-infrared 200 mm CMOS architecture

2021 ◽  
Author(s):  
Mark Dong ◽  
Genevieve Clark ◽  
Andrew J. Leenheer ◽  
Matthew Zimmermann ◽  
Daniel Dominguez ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Speed ◽  
Large Scale ◽  
Near Infrared ◽  
Response Times ◽  
Photonic Integrated Circuits ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Shifters ◽  
Oxide Semiconductor

AbstractRecent advances in photonic integrated circuits have enabled a new generation of programmable Mach–Zehnder meshes (MZMs) realized by using cascaded Mach–Zehnder interferometers capable of universal linear-optical transformations on N input/output optical modes. MZMs serve critical functions in photonic quantum information processing, quantum-enhanced sensor networks, machine learning and other applications. However, MZM implementations reported to date rely on thermo-optic phase shifters, which limit applications due to slow response times and high power consumption. Here we introduce a large-scale MZM platform made in a 200 mm complementary metal–oxide–semiconductor foundry, which uses aluminium nitride piezo-optomechanical actuators coupled to silicon nitride waveguides, enabling low-loss propagation with phase modulation at greater than 100 MHz in the visible–near-infrared wavelengths. Moreover, the vanishingly low hold-power consumption of the piezo-actuators enables these photonic integrated circuits to operate at cryogenic temperatures, paving the way for a fully integrated device architecture for a range of quantum applications.

Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses

2003 ◽  
Vol 15 (2) ◽  
pp. 208-218 ◽  
Author(s):  
Yusuke Kanazawa ◽  
◽  
Tetsuya Asai ◽  
Yoshihito Amemiya
Keyword(s):  
Neural Network ◽  
Large Scale ◽  
Spiking Neurons ◽  
Oxide Semiconductor ◽  
Competitive Neural Network ◽  
Brain Functions ◽  
Analog Cmos ◽  
Integration Architecture ◽  
Dynamic Synapses ◽  
The Brain

We discuss the integration architecture of spiking neurons, predicted to be next-generation basic circuits of neural processor and dynamic synapse circuits. A key to development of a brain-like processor is to learn from the brain. Learning from the brain, we try to develop circuits implementing neuron and synapse functions while enabling large-scale integration, so large-scale integrated circuits (LSIs) realize functional behavior of neural networks. With such VLSI, we try to construct a large-scale neural network on a single semiconductor chip. With circuit integration now reaching micron levels, however, problems have arisen in dispersion of device performance in analog IC and in the influence of electromagnetic noise. A genuine brain computer should solve such problems on the network level rather than the element level. To achieve such a target, we must develop an architecture that learns brain functions sufficiently and works correctly even in a noisy environment. As the first step, we propose an analog circuit architecture of spiking neurons and dynamic synapses representing the model of artificial neurons and synapses in a form closer to that of the brain. With the proposed circuit, the model of neurons and synapses can be integrated on a silicon chip with metal-oxide-semiconductor (MOS) devices. In the sections that follow, we discuss the dynamic performance of the proposed circuit by using a circuit simulator, HSPICE. As examples of networks using these circuits, we introduce a competitive neural network and an active pattern recognition network by extracting firing frequency information from input information. We also show simulation results of the operation of networks constructed with the proposed circuits.

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