scholarly journals Area Efficient Implementation of MTI Processing Module on a Reconfigurable Platform

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Munaza Yousuf ◽  
Arshad Aziz ◽  
Riaz Mahmud
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Digital Design ◽  
Radar Signal ◽  
Field Programmable ◽  
Processing Module ◽  
Reconfigurable Platform ◽  
High Level ◽  
High Processing ◽  
Area Efficient

This paper presents an area efficient Field Programmable Gate Array (FPGA) based digital design of a processing module for MTI radar. Signal contaminated with noise and clutter is modelled to test the efficacy of the design algorithms. For flexibility of design and to achieve optimized results, we have combined the high-level utility of MATLAB with the flexibility and optimization on FPGA for this implementation. Two- and three-pulse cancellers are chosen for design due to its simplicity in both concept and implementation. The results obtained are efficient in terms of enhanced throughput per Slice (TPA) of 1.146, that is, occupying fewer area resources on hardware while achieving optimized speed. The outcomes show that this design of MTI radar processor has many advantages, such as high processing precision, strong processing ability, real time, and low cost. All these advantages greatly contribute to the design requirements and make it appropriate for the application of high-speed signal processing.

Based on FPGA Intelligent Physiological Parameters Acquisition

2013 ◽  
Vol 344 ◽  
pp. 107-110
Author(s):  
Shun Ren Hu ◽  
Ya Chen Gan ◽  
Ming Bao ◽  
Jing Wei Wang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Physiological Parameters ◽  
Sensor Data ◽  
Low Power Consumption ◽  
Physiological Signal ◽  
Pulse Sensor ◽  
Monitoring Applications ◽  
Field Programmable ◽  
Design Ideas

For the physiological signal monitoring applications, as a micro-controller based on field programmable gate array (FPGA) physiological parameters intelligent acquisition system is given, which has the advantages of low cost, high speed, low power consumption. FPGA is responsible for the completion of pulse sensor, the temperature sensor, acceleration sensor data acquisition and serial output and so on. Focuses on the design ideas and architecture of the various subsystems of the whole system, gives the internal FPGA circuit diagram of the entire system. The whole system is easy to implement and has a very good promotional value.

A Primer for Telemetry Interfacing in Accordance with NASA Standards Using Low Cost FPGAs

2016 ◽  
Vol 05 (01) ◽  
pp. 1640002
Author(s):  
Jake McCoy ◽  
Ted Schultz ◽  
James Tutt ◽  
Thomas Rogers ◽  
Drew Miles ◽  
...  
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Photon Counting ◽  
Sounding Rocket ◽  
Photon Counting Detector ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Custom Hardware ◽  
Commercial Off The Shelf ◽  
Main Component

Photon counting detector systems on sounding rocket payloads often require interfacing asynchronous outputs with a synchronously clocked telemetry (TM) stream. Though this can be handled with an on-board computer, there are several low cost alternatives including custom hardware, microcontrollers and field-programmable gate arrays (FPGAs). This paper outlines how a TM interface (TMIF) for detectors on a sounding rocket with asynchronous parallel digital output can be implemented using low cost FPGAs and minimal custom hardware. Low power consumption and high speed FPGAs are available as commercial off-the-shelf (COTS) products and can be used to develop the main component of the TMIF. Then, only a small amount of additional hardware is required for signal buffering and level translating. This paper also discusses how this system can be tested with a simulated TM chain in the small laboratory setting using FPGAs and COTS specialized data acquisition products.

scholarly journals ANALYSIS OF EFFECTS OF USING 9/7 WAVELET COEFFICIENTS IN MULTI-RESOLUTION ANALYSIS

2016 ◽  
Vol 2 (1) ◽  
Author(s):  
Manish Sharma ◽  
Prof. Sonu Lal
Keyword(s):  
High Speed ◽  
Utilization Efficiency ◽  
Parallel Structure ◽  
Discrete Wavelet ◽  
Distributed Arithmetic ◽  
Fpga Design ◽  
Multi Resolution Analysis ◽  
Field Programmable ◽  
On Chip ◽  
Area Efficient

Conventional distributed arithmetic (DA) is popular in field programmable gate array (FPGA) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, we describe high speed area efficient 1-D discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA) Technique. Being area efficient architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. This architecture supports any size of image pixel value and any level of decomposition. The parallel structure has 100% hardware utilization efficiency.

scholarly journals Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

2019 ◽  
Vol 8 (4) ◽  
pp. 10189-10198 ◽  
Keyword(s):  
High Speed ◽  
Complex Multiplication ◽  
Cmos Technology ◽  
Hardware Complexity ◽  
Processing Application ◽  
Point Support ◽  
Multiplication Operation ◽  
Field Programmable ◽  
Cadence Tool ◽  
Area Efficient

Fast Fourier Transform (FFT) acts as an element in the high-speed signal processing application, which involves the following subsequent operations, namely complex addition, complex subtraction and complex multiplication. Due to the complex multiplication operation, the FFT structures lead to more hardware demand. Hence, this work introduces an area-efficient various N-point support radix-2 and radix-22 FFT structure by using proposed modified butterfly units and radix-2/22 butterfly unit. The proposed modified butterfly units are used to reduce the number of complex multipliers effectively. For this reason, it is using for certain conditions in FFT design instead of existing radix-2/22 butterfly unit. Further, the proposed design supported to perform various size of FFT in a single architecture without increasing the extra element demand. Moreover, the proposed FFT structure designed and implemented using a Xilinx Virtex-6 Field-Programmable Gate Array (FPGA) device (6vcx75tff484-2) and Cadence tool with 45nm CMOS technology. The implementation results demonstrate that the proposed N-point (N=16, 32 and 64) DIF-FFT design attains the less hardware complexity when compared with existing multi-mode FFT design. Then the proposed area-efficient 16-point, 32-point and 64-point radix-2 FFT architectures reduce the total area by 20.99%, 11% and 4.9% respectively. As well, the proposed area-efficient 16-point, 32-point and 64-point radix-22 FFT architectures reduce the total area by 32%, 19% and 11% respectively.

FPGA TECHNOLOGY IN PROCESS TOMOGRAPHY

2016 ◽  
Vol 78 (7-4) ◽  
Author(s):  
Lean Thiam Siow ◽  
Mohd Hafiz Fazalul Rahiman ◽  
Ruzairi Abdul Rahim ◽  
Mohd Shukry Abdul Majid ◽  
Salman Sayyidi Hamzah ◽  
...  
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Gate Arrays ◽  
Tomography System ◽  
Process Tomography ◽  
Ultrasonic Process ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Future Work

The aims of this paper are to provide a review of the process tomography applications employing field programmable gate arrays (FPGA) and to understand current FPGA related researches, in order to seek for the possibility to applied FPGA technology in an ultrasonic process tomography system. FPGA allows users to implement complete systems on a programmable chip, meanwhile, five main benefits of applying the FPGA technology are performance, time to market, cost, reliability, and long-term maintenance. These advantages definitely could help in the revolution of process tomography, especially for ultrasonic process tomography and electrical process tomography. Future work is focused on the ultrasonic process tomography for chemical process column investigation using FPGA for the aspects of low cost, high speed and reconstructed image quality.

scholarly journals Space-time trellis codes: Field programmable gate array approach

2020 ◽  
Vol 9 (3) ◽  
pp. 213
Author(s):  
Mallikarjuna Gowda C. P. ◽  
Raju Hajare
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Space Time ◽  
Trellis Codes ◽  
Software Environment ◽  
High Data ◽  
Field Programmable ◽  
Gate Array

This paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment.

scholarly journals Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1952
Author(s):  
Eva M. Cirugeda-Roldán ◽  
María Sofía Martínez-García ◽  
Alberto Sanchez ◽  
Angel de Castro
Keyword(s):  
High Speed ◽  
Power Converters ◽  
Low Cost ◽  
Hardware In The Loop ◽  
Main Design ◽  
Gate Arrays ◽  
The World ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Area Optimization

Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for the IEEE NF libraries of VHDL-2008 was included. This work presents an exhaustive evaluation of the performance of Vivado 2020.2 in terms of area and speed using the native IEEE libraries of VHDL-2008 regarding NF. Results show that even though fixed-point NFs optimize area and speed, if a user prefers the use of floating-point NFs, with this new release, it can be synthesized—which could not be done in previous versions of Vivado. Although support for the native IEEE libraries of VHDL-2008 was included in Vivado 2020.2, it still lacks some issues regarding NF conversion during synthesis while support for simulation is not yet included.

scholarly journals The development of real-time communication network based on Zigbee and Ethernet for Photovoltaic systems

2014 ◽  
Vol 17 (1) ◽  
pp. 5-15
Author(s):  
Dung Quoc Phan ◽  
Dat Ngoc Dao ◽  
Hiep Chi Le
Keyword(s):  
Communication Network ◽  
Real Time ◽  
High Speed ◽  
Large Scale ◽  
Low Cost ◽  
Photovoltaic System ◽  
Solar Inverter ◽  
Ethernet Controller ◽  
Controller Board ◽  
High Level

In a large system with a lot of distribution solar sources which are all connected to the national grid, a communication system becomes the important part for data acquisition in order to control the whole system stable and efficiency. To deal with this challenge, this paper presents a solution based on Zigbee and Ethernet communication standard. Zigbee standard was created to be a specification of a high level wireless communication protocol which is not only secure, reliable, simple but also low cost and low power. With Zigbee, we can create a communication network for hundreds to thousands of mini solar sources in a large scale of photovoltaic system. Ethernet is a high speed wired communication technology that is used widely in industrial and automatic applications. Together Zigbee and Ethernet bring to us a real-time communication solution for the system. In the experiment prototype of this paper, we use the CC2530ZNP-Mini Kit to create a simple network includes one coordinate and one end device for the first step. The end device was configured to get current and voltage values from a 3-phase grid-connected solar inverter 800Wpk and then sends the values to the coordinate. After the coordinate received data, it would send them to an Ethernet controller board. To display the data through Ethernet, we embedded a web server on the Ethernet controller board. By this way, the data was easy to visualize and supervised by using any web browser.

EVALUATION STUDY OF SYSTOLIC ARRAY PROCESSORS OPTIMIZATION AND MAPPING ON k-LUT FPGA DEVICES

2013 ◽  
Vol 22 (04) ◽  
pp. 1350025
Author(s):  
STAVROS P. DOKOUZYANNIS ◽  
ARGIRIS P. MOKIOS
Keyword(s):  
Systolic Array ◽  
High Speed ◽  
Large Scale ◽  
Logic Synthesis ◽  
Evaluation Study ◽  
Optimization Approach ◽  
Array Processors ◽  
Field Programmable ◽  
High Level ◽  
Selection Of

This paper analyzes the design automation of embedded Systolic Array Processors (SAPs), into large scale Field Programmable Gate Array (FPGA) devices. SAPs are hardware implementations of a class of iterative, high-level language algorithms, for applications where the high-speed of processing has the principal meaning of a design. Embedding SAPs onto FPGAs is a complex process. The optimization phase in this process reduces the SAP significantly, thus less FPGA area is occupied by the embedded design, without any loss in the final performance. The present paper examines the effect of Projection Vectors (PVs) and Task Scheduling Vectors (TSVs) on the optimization process. Two optimization approaches are examined, namely technology mapping using FlowMap and Flowpack algorithms and optimization via logic synthesis using Xilinx Synthesis Tool. The multiplication of matrices, with entries being up to 32-bit integer vectors, has been taken as a sample space for the experiments conducted. The results, confirm that the selection of PV and TSV greatly affects the number of input/output signal connections of the FPGA, while the selection of an optimization approach affects the final number of logic resources occupied on the targeted device.

Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL

2019 ◽  
Vol 08 (03) ◽  
pp. 1950008 ◽  
Author(s):  
Haomiao Wang ◽  
Prabu Thiagaraj ◽  
Oliver Sinnen
Keyword(s):  
High Speed ◽  
Design Space ◽  
Hardware Accelerators ◽  
Gate Arrays ◽  
Fast Prototyping ◽  
Multiple Input ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Square Kilometer Array ◽  
High Level

Field-Programmable Gate Arrays (FPGAs) are widely used in the central signal processing design of the Square Kilometer Array (SKA) as hardware accelerators. The frequency domain acceleration search (FDAS) module is an important part of the SKA1-MID pulsar search engine. To develop for a yet to be finalized hardware, for cross-discipline interoperability and to achieve fast prototyping, OpenCL as a high-level FPGA synthesis approaches employed to create the sub-modules of FDAS. The FT convolution and the harmonic-summing plus some other minor sub-modules are elements in the FDAS module that have been well-optimized separately before. In this paper, we explore the design space of combining well-optimized designs, dealing with the ensuing need to trade-off and compromise. Pipeline computing is employed to handle multiple input arrays at high speed. The hardware target is to employ multiple high-end FPGAs to process the combined FDAS module. The results show interesting consequences, where the best individual solutions are not necessarily the best solutions for the speed of a pipeline where FPGA resources and memory bandwidth need to be shared. By proposing multiple buffering techniques to the pipeline, the combined FDAS module can achieve up to 2[Formula: see text] speedup over implementations without pipeline computing. We perform an extensive experimental evaluation on multiple high-end FPGA cards hosted in a workstation and compare to a technology comparable mid-range GPU.

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