Based on FPGA Intelligent Physiological Parameters Acquisition

2013 ◽  
Vol 344 ◽  
pp. 107-110
Author(s):  
Shun Ren Hu ◽  
Ya Chen Gan ◽  
Ming Bao ◽  
Jing Wei Wang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Physiological Parameters ◽  
Sensor Data ◽  
Low Power Consumption ◽  
Physiological Signal ◽  
Pulse Sensor ◽  
Monitoring Applications ◽  
Field Programmable ◽  
Design Ideas

For the physiological signal monitoring applications, as a micro-controller based on field programmable gate array (FPGA) physiological parameters intelligent acquisition system is given, which has the advantages of low cost, high speed, low power consumption. FPGA is responsible for the completion of pulse sensor, the temperature sensor, acceleration sensor data acquisition and serial output and so on. Focuses on the design ideas and architecture of the various subsystems of the whole system, gives the internal FPGA circuit diagram of the entire system. The whole system is easy to implement and has a very good promotional value.

A Primer for Telemetry Interfacing in Accordance with NASA Standards Using Low Cost FPGAs

2016 ◽  
Vol 05 (01) ◽  
pp. 1640002
Author(s):  
Jake McCoy ◽  
Ted Schultz ◽  
James Tutt ◽  
Thomas Rogers ◽  
Drew Miles ◽  
...  
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Photon Counting ◽  
Sounding Rocket ◽  
Photon Counting Detector ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Custom Hardware ◽  
Commercial Off The Shelf ◽  
Main Component

Photon counting detector systems on sounding rocket payloads often require interfacing asynchronous outputs with a synchronously clocked telemetry (TM) stream. Though this can be handled with an on-board computer, there are several low cost alternatives including custom hardware, microcontrollers and field-programmable gate arrays (FPGAs). This paper outlines how a TM interface (TMIF) for detectors on a sounding rocket with asynchronous parallel digital output can be implemented using low cost FPGAs and minimal custom hardware. Low power consumption and high speed FPGAs are available as commercial off-the-shelf (COTS) products and can be used to develop the main component of the TMIF. Then, only a small amount of additional hardware is required for signal buffering and level translating. This paper also discusses how this system can be tested with a simulated TM chain in the small laboratory setting using FPGAs and COTS specialized data acquisition products.

scholarly journals Integration of highly anisotropic multiferroic BaTiO3–Fe nanocomposite thin films on Si towards device applications

2020 ◽  
Vol 2 (9) ◽  
pp. 4172-4178
Author(s):  
Matias Kalaswad ◽  
Bruce Zhang ◽  
Xuejing Wang ◽  
Han Wang ◽  
Xingyao Gao ◽  
...  
Keyword(s):  
Thin Films ◽  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Low Cost ◽  
Low Power Consumption ◽  
Silicon Substrates ◽  
Critical Step ◽  
Nanocomposite Thin Films ◽  
Device Applications

Integration of highly anisotropic multiferroic thin films on silicon substrates is a critical step towards low-cost devices, especially high-speed and low-power consumption memories.

Design of Process Controller Based on PCI Interface and CPLD Technology

2012 ◽  
Vol 614-615 ◽  
pp. 1562-1565
Author(s):  
Yu Sen Li ◽  
Ying Sun
Keyword(s):  
Real Time ◽  
High Speed ◽  
Low Cost ◽  
Pulse Signal ◽  
Pci Bus ◽  
Signal Acquisition ◽  
Real Time Control ◽  
Time Control ◽  
Interface Chip ◽  
Design Ideas

In order to realize the sensor signal acquisition and analysis of data, according to data acquisition system design ideas of the PCI bus, applying to CPLD complex programmable controller and CH365 interface chip and combined with the actual needs of data collection ,designed a kind of low cost, high speed process controller. CPLD realizes data cache control and the control of reading. This design can gather 16 roads analog signals and real-time pulse signal of 8 roads on the same time, which includes a 16-bit digital output channel and a 32-bit counter, could be used in the real-time control.

Developments in Efficient Antenna Designs Using EBG Structures

2017 ◽  
pp. 34-84
Author(s):  
Naveen Jaglan ◽  
Samir Dev Gupta ◽  
Binod Kumar Kanaujia ◽  
Shweta Srivastava
Keyword(s):  
High Speed ◽  
Short Range ◽  
Low Cost ◽  
Federal Communication Commission ◽  
Antenna Design ◽  
Low Power Consumption ◽  
Impedance Bandwidth ◽  
Antenna Performance ◽  
X Band ◽  
Uwb Applications

Since 2002, when the Federal Communication Commission (FCC) released the bandwidth 3.1-10.6 GHz, there has been increasing interest in the use of UWB systems because of their low power consumption, low cost, precise positioning and promising candidate for short-range high-speed indoor data communications. Planar circular monopoles like designs are a good example for UWB applications due to their merits such as ease of fabrication, Acceptable radiation pattern, and large impedance bandwidth. However, some narrowband systems also operate in this frequency like WiMAX, WLAN and X-Band satellite downlink communication band etc. cause interference in UWB range. To overcome any interference with these systems it is desirable to design UWB antenna with band notches. However, most techniques of obtaining notches uses antenna design specific approaches therefore EBG structures can be used to obtain single and multi-notch antennas. The technique used for obtaining notches using EBG is antenna design independent and can be applied to most of the antennas without compromising antenna performance.

FPGA TECHNOLOGY IN PROCESS TOMOGRAPHY

2016 ◽  
Vol 78 (7-4) ◽  
Author(s):  
Lean Thiam Siow ◽  
Mohd Hafiz Fazalul Rahiman ◽  
Ruzairi Abdul Rahim ◽  
Mohd Shukry Abdul Majid ◽  
Salman Sayyidi Hamzah ◽  
...  
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Gate Arrays ◽  
Tomography System ◽  
Process Tomography ◽  
Ultrasonic Process ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Future Work

The aims of this paper are to provide a review of the process tomography applications employing field programmable gate arrays (FPGA) and to understand current FPGA related researches, in order to seek for the possibility to applied FPGA technology in an ultrasonic process tomography system. FPGA allows users to implement complete systems on a programmable chip, meanwhile, five main benefits of applying the FPGA technology are performance, time to market, cost, reliability, and long-term maintenance. These advantages definitely could help in the revolution of process tomography, especially for ultrasonic process tomography and electrical process tomography. Future work is focused on the ultrasonic process tomography for chemical process column investigation using FPGA for the aspects of low cost, high speed and reconstructed image quality.

scholarly journals Space-time trellis codes: Field programmable gate array approach

2020 ◽  
Vol 9 (3) ◽  
pp. 213
Author(s):  
Mallikarjuna Gowda C. P. ◽  
Raju Hajare
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Space Time ◽  
Trellis Codes ◽  
Software Environment ◽  
High Data ◽  
Field Programmable ◽  
Gate Array

This paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment.

scholarly journals Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1952
Author(s):  
Eva M. Cirugeda-Roldán ◽  
María Sofía Martínez-García ◽  
Alberto Sanchez ◽  
Angel de Castro
Keyword(s):  
High Speed ◽  
Power Converters ◽  
Low Cost ◽  
Hardware In The Loop ◽  
Main Design ◽  
Gate Arrays ◽  
The World ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Area Optimization

Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for the IEEE NF libraries of VHDL-2008 was included. This work presents an exhaustive evaluation of the performance of Vivado 2020.2 in terms of area and speed using the native IEEE libraries of VHDL-2008 regarding NF. Results show that even though fixed-point NFs optimize area and speed, if a user prefers the use of floating-point NFs, with this new release, it can be synthesized—which could not be done in previous versions of Vivado. Although support for the native IEEE libraries of VHDL-2008 was included in Vivado 2020.2, it still lacks some issues regarding NF conversion during synthesis while support for simulation is not yet included.

scholarly journals FPGA Implementation of DTCWT and PCA Based Watermarking Technique

2018 ◽  
Vol 7 (2) ◽  
pp. 82
Author(s):  
M. S. Sudha ◽  
T. C. Thanuja
Keyword(s):  
Wavelet Transform ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Implementation ◽  
Image Watermarking ◽  
Software Implementation ◽  
Low Power Consumption ◽  
Complex Wavelet Transform ◽  
System Generator ◽  
Field Programmable

The hardware implementation of the image watermarking algorithm offers numerous distinct advantages over the software implementation in terms of low power consumption, less area usage and reliability. The advantages of Dual Tree Complex Wavelet Transform (DTCWT) and Principle Component Analysis (PCA) techniques are extracted to improve the robustness and perceptibility. The hardware watermarking solution is more economical, because adding the component only takes up a small dedicated area of silicon. The algorithm is developed and simulated using Matlab, Simulink and system generator. The implementation is carried out using Spartan 6 Diligent Atlys Field Programmable Gate array (FPGA). The architecture uses 256 slice registers, 257 slice Look Up Tables (LUT’s) and 47 I/O pins. It also meets the requirement of high speed architecture with a delay of 1.328ns and an operating frequency of 549.451MHz.

scholarly journals 10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1665
Author(s):  
Paolo Visconti ◽  
Stefano Capoccia ◽  
Eugenio Venere ◽  
Ramiro Velázquez ◽  
Roberto de Fazio
Keyword(s):  
Communication System ◽  
High Speed ◽  
Low Cost ◽  
Scientific Article ◽  
Clock Period ◽  
Data Packets ◽  
Data Throughput ◽  
Field Programmable ◽  
Encryption Decryption ◽  
Base Band

The security of communication and computer systems is an increasingly important issue, nowadays pervading all areas of human activity (e.g., credit cards, website encryption, medical data, etc.). Furthermore, the development of high-speed and light-weight implementations of the encryption algorithms is fundamental to improve and widespread their application in low-cost, low-power and portable systems. In this scientific article, a high-speed implementation of the AES-128 algorithm is reported, developed for a short-range and high-frequency communication system, called Wireless Connector; a Xilinx ZCU102 Field Programmable Gate Array (FPGA) platform represents the core of this communication system since manages all the base-band operations, including the encryption/decryption of the data packets. Specifically, a pipelined implementation of the Advanced Encryption Standard (AES) algorithm has been developed, allowing simultaneous processing of distinct rounds on multiple successive plaintext packets for each clock period and thus obtaining higher data throughput. The proposed encryption system supports 220 MHz maximum operating frequency, ensuring encryption and decryption times both equal to only 10 clock periods. Thanks to the pipelined approach and optimized solutions for the Substitute Bytes operation, the proposed implementation can process and provide the encrypted packets each clock period, thus obtaining a maximum data throughput higher than 28 Gbit/s. Also, the simulation results demonstrate that the proposed architecture is very efficient in using hardware resources, requiring only 1631 Configurable Logic Blocks (CLBs) for the encryption block and 3464 CLBs for the decryption one.

scholarly journals Safety Helmet Implementation with Centralized Information System on Remote Monitoring Applications

2018 ◽  
pp. 1
Author(s):  
Alvinas Deva Sih Illahi ◽  
Anatasya Bella ◽  
Sugondo Hadiyoso ◽  
Suci Aulia
Keyword(s):  
Temperature Sensor ◽  
Sensor Data ◽  
Test Results ◽  
Standard Equipment ◽  
Safety Glass ◽  
Pulse Sensor ◽  
Standard Tool ◽  
Monitoring Applications ◽  
Accuracy Level ◽  
Sensor Temperature

Personal Protective Equipment (PPE) is standard equipment that required to ensure safety of workers. PPE equipment that used during work such as: Safety helmet, safety glass, and ear plug. PPE that being used by workers doesn’t informative yet, only serve as personal protective so evacuation prevention still looks difficult to do prior accident happened. In this research, Safety Helmet Project has been implemented with pulse sensor, temperature sensor, carbon monoxide gas sensor, and transmission media which able transmitting data to control and monitoring center. The system also supports multiuser monitoring applications that can be accessed simultaneously through the internet network. Based on test results, the comparison of measurement gap with standard tool has been obtained as temperature sensor is 0,07%, heart sensor is ± 4%. Accuracy level for temperature sensor and heart rate are 99,67% and 95,45% by various condition of test. Another test is delay of the transmitting sensor data to the website around ± 10 seconds and controlling around ± 5 seconds.

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