LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION

10.6036/10214 ◽  
2021 ◽  
Vol 96 (5) ◽  
pp. 505-511
Author(s):  
LOGANATHAN MOHANA KANNAN ◽  
DHANASKODI DEEPA
Keyword(s):  
Image Processing ◽  
Biomedical Imaging ◽  
Large Scale ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Vlsi Design ◽  
Fir Filter ◽  
Vedic Multiplier ◽  
Imaging Application ◽  
Processing Techniques

Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;

scholarly journals Design of 32 Tap Finite Impulse Response Filter using Vedic Multiplier and KoggeStone Adder

2019 ◽  
Vol 8 (2) ◽  
pp. 6138-6141
Keyword(s):  
Filter Design ◽  
Finite Impulse Response ◽  
Software Tool ◽  
Propagation Delay ◽  
Fir Filter ◽  
Filter Synthesis ◽  
Look Ahead ◽  
Vedic Multiplier ◽  
Ripple Carry Adder ◽  
Effective Performance

32 tap FIR Filter is designed utilizing Vedic multiplier and Kogge stone adder. Effective performance is important for FIR Filter design due to increasing complexity. Two basic opertaions of FIR Filter are multiplication and addition. So, for multiplication, vedic multiplier is used and addition is performed by KS adder which is faster than other adders like Ripple carry adder, Look ahead carry adder, Carry select adder etc. K S adder is used to overcome problem of carry propagation. The objective is to minimize the propagation delay i.e increasing the speed of filter. Synthesis & simulation is done by Xilinx ISE 14.7 software tool using VHDL.

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
C. Srinivasa Murthy ◽  
K. Sridevi
Keyword(s):  
Energy Efficiency ◽  
Power Dissipation ◽  
Software Defined Radio ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Software Tool ◽  
Building Blocks ◽  
Fir Filter ◽  
Content Type ◽  
Filter Length

Purpose In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters. Design/methodology/approach The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer. Findings Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively. Originality/value The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit

2021 ◽  
pp. 2250016
Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Speech Processing ◽  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Low Power Design ◽  
Fir Filter ◽  
Efficient Design ◽  
Power Efficient

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

Approximate Compressor-Based Multiplier Design Methodology for Error-Resilient Digital Signal Processing

2020 ◽  
Vol 29 (14) ◽  
pp. 2050233
Author(s):  
Zhixi Yang ◽  
Xianbin Li ◽  
Jun Yang
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Digital Signal Processing ◽  
Resource Utilization ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Electrical Performance ◽  
Approximate Computing ◽  
Dsp Applications

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25[Formula: see text]dB for image processing; similarly, with a decrease of 0.3[Formula: see text]dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

scholarly journals FIR Filter Design using Finfets at 22nm Technology

2019 ◽  
Vol 9 (2) ◽  
pp. 1292-1295
Keyword(s):  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Fir Filters ◽  
Short Channel ◽  
Channel Effects ◽  
Complex Circuits ◽  
Fir Filter Design

Finite Impulse Response (FIR) filters are the most significantdevice in digital signal processing.In many Digital Signal Processing applications like wireless communication, image and video processing FIR filters are used.Digital FIR filters primarily consists of multipliers, adders and delay elements. Area, power optimization and speed are the key design metrics of FiniteImpulse Response filter.As more electronic devices are battery operated, power consumption constraint becomes a major issue. Multipliers are the core of FIR filters. They consume a lot of energy and are generally complex circuits. With each new process technologies, the short channel effects limit the performance of FIR filters at nano regime. Various architectures have been proposed to enhance the performance of FIR filter. In this paper, FIR filter is designed using FINFETs at 22nm technology using Hspice software.

A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware–Software Co-Design

2019 ◽  
Vol 29 (01) ◽  
pp. 2050014
Author(s):  
C. Ranjith ◽  
S. P. Joy Vasantha Rani
Keyword(s):  
Hardware Implementation ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Adaptive Genetic Algorithm ◽  
Ip Core ◽  
Complete Evaluation ◽  
Flexible System ◽  
On Chip ◽  
The Impact

Recent studies show the impact of genetic algorithms (GA) in the design of evolutionary finite impulse response (FIR) filters. Studies have shown hardware and software method of GA implementation for design. Hardware method improves speed due to parallelism, pipelining and the absence of the function calls compared to software implementation. But area constraint was the main issue of hardware implementation. Therefore, this paper illustrates a hardware–software co-design concept to implement an Adaptive GA processor (AGAP) for FIR filter design. The architecture of AGAP uses adaptive crossover and mutation probabilities to speed up the convergence of the GA process. The AGAP architecture was implemented using Verilog Hardware Description Language (HDL) and instantiated as a custom intellectual property (IP) core to the soft-core MicroBlaze processor of Spartan 6 (XC6SLX45-3CSG324I) FPGA. The MicroBlaze processor controls the AGAP IP core and other interfaces using Embedded C programs. The experiment demonstrated a significant 134% improvement in speed over hardware implementation but with a marginal increase in area. The complete evaluation and evolution of the filter coefficients were executed on a single FPGA. The system on chip (SoC) concept enables a robust and flexible system.

Implementation of the Finite Impulse Response (FIR) Filter on the DSK TMS320C6713 Transceiver Using Windowing Techniques

2018 ◽  
Vol 6 (1) ◽  
pp. 1-8
Author(s):  
Adella Acqha Vico Addina
Keyword(s):  
Filter Design ◽  
Finite Impulse Response ◽  
Bandpass Filters ◽  
Fir Filter ◽  
Test Results ◽  
Rectangular Window ◽  
Filter Performance ◽  
Highpass Filter ◽  
Low Pass ◽  
High Pass

In this study, implementing the FIR filter with the Blackman window and Rectangular window methods with the types of low pass, highpass, and bandpass filters using 2 DSK TMS320C6713 boards as sender (Tx) and receiver (Rx) using the code composer studio (CCS) V software program. .3.1, which will then be displayed on Matlab to observe the output results. From the test results, data will be obtained which are then analyzed to determine the filter performance of the design results and the real implementation results using the DSK TMS320C6713. The results showed that the design of the low pass, high pass and bandpass filters was in accordance with the desired specifications, although in the highpass filter design, the filter results were still incomplete.

VLSI Design and Comparison of DA and LMS Based Reconfigurable FIR Filter

2016 ◽  
Vol 5 (2) ◽  
pp. 124
Author(s):  
P. Hemanthkumar ◽  
Y. Sai Kiran ◽  
V. Nava Teja
Keyword(s):  
Performance Metrics ◽  
Finite Impulse Response ◽  
Vlsi Design ◽  
Fir Filter ◽  
Inner Product ◽  
Distributed Arithmetic ◽  
Power Efficient ◽  
Consumption Energy ◽  
The Look ◽  
Suitable Area

<p>Here, we exhibit the design optimization of one- and two-dimensional fully-pipelined computing structures for area-delay-power-efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-based inner-product computation. This plan is found to offer a flexible choice of the address length of the look-up-tables (LUT) for DA-based computation to determine suitable area-time trade-off. It is seen that by using smaller address-lengths for DA-based computing units, it is possible to decrease the memory-size but on the other side that leads to increase of adder complexity and the latency. For efficient DA-based realization of FIR filters of different orders, the flexible linear systolic design is implemented on a Xilinx Virtex-E XCV2000E FPGA using a hybrid combination of Handel-C and parameterizable VHDL cores. Various key performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, energy density and energy throughput are estimated for different filter orders and address-lengths. Obtained results on analysis shows that performance metrics of the proposed implementation is broadly in line with theoretical expectations. We have seen that the choice of address-length M=4 gives the best of area-delay power-efficient realizations of the FIR filter for different filter orders. Moreover, the proposed FPGA implementation is found to involve significantly less area-delay complexity compared with the existing DA-based implementations of FIR filter.</p>

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