Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic

2016 ◽  
Vol 25 (07) ◽  
pp. 1650073 ◽  
Author(s):  
Subodh Kumar Singhal ◽  
Basant Kumar Mohanty
Keyword(s):  
Variable Coefficient ◽  
Complexity Analysis ◽  
Finite Impulse Response ◽  
Clock Cycle ◽  
Theoretical Estimate ◽  
Parallel Architecture ◽  
Block Size ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Filter Length

In this paper, we performed the complexity analysis of fixed-coefficient and variable-coefficient distributed arithmetic (DA)-based finite impulse response (FIR) filter structures to observe the effect of LUT decomposition on the area complexity of DA structure. The complexity analysis reveals that the area complexity of different units of DA FIR filter structure does not increase proportionately with the level of parallelism. An appropriate selection of LUT decomposition factor, and introducing higher level of parallelism in the computation could improve the area-delay efficiency of both fixed-coefficient and variable-coefficient DA-based FIR structures. Based on these findings, we have proposed bit-parallel block-based DA structures, for fixed-coefficient and variable-coefficient FIR. The proposed structures process one block of input samples and produce one block of outputs in every clock cycle. Theoretical estimate shows that the proposed fixed-coefficient structure, for block-size 8 and filter-length 32, involves eight times more ROM-LUT words, eight times more adders, two less registers, and offers eight times higher throughput-rate than the existing similar structure. For the same block-size and filter-length, the proposed variable-coefficient structure involves 7.2 times more adders, the same number of registers, eight times more MUXes, and offers eight times higher throughput than the best available similar structure. Synthesis result shows that the proposed fixed-coefficient structure for block-size 8 and filter-length 32 involve 47% less area delay product (ADP) and 42% less energy per sample (EPS) than the existing structure and offers nearly eight times higher throughput than others. For the same block-size and filter-length, the proposed structure for variable-coefficient FIR involves 71% less ADP and 65% less EPS than the similar existing structures.

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
C. Srinivasa Murthy ◽  
K. Sridevi
Keyword(s):  
Energy Efficiency ◽  
Power Dissipation ◽  
Software Defined Radio ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Software Tool ◽  
Building Blocks ◽  
Fir Filter ◽  
Content Type ◽  
Filter Length

Purpose In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters. Design/methodology/approach The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer. Findings Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively. Originality/value The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

ECG Noise Removal Using Modified Distributed Arithmetic Based Finite Impulse Response Filter

2021 ◽  
Vol 11 (5) ◽  
pp. 1444-1452
Author(s):  
A. Uma ◽  
P. Kalpana
Keyword(s):  
Finite Impulse Response ◽  
Signal To Noise Ratio ◽  
Human Life ◽  
Stress Test ◽  
Noise Removal ◽  
Fir Filter ◽  
Signal Acquisition ◽  
Distributed Arithmetic ◽  
Hardware Resource ◽  
Baseline Wander

ECG monitoring is essential to support human life. During signal acquisition, the signals are contaminated by various noises that occur due to different sources. This paper focuses on Baseline wander and Muscle Artifact noise removal using Distributed Arithmetic (DA) based FIR filters. An area-efficient modified DA based FIR filter consists of LUT-less structure and used for noise removal. The performance of the modified DA based FIR filter is compared with the conventional DA FIR filter. An arbitrary real-time ECG record is taken from MIT-BIH database and Baseline Wander noise, Muscle artifact noises are taken from MIT-BIH noise stress test database. The performance of both filters is evaluated in terms of output Signal to Noise Ratio (SNR) and Mean Square Error (MSE). For Baseline wander noise removal, the modified DA based FIR filter produces high output SNR and also low MSE of 76.6% than the conventional filter. Similarly, for Muscle Artifact noise removal, it produces high SNR, and MSE is reduced to 73.8%. A modified DA based FIR filter is synthesized for the target FPGA device Spartan3E XC3s2000-4fg900 and hardware resource utilization is presented.

VLSI Design and Comparison of DA and LMS Based Reconfigurable FIR Filter

2016 ◽  
Vol 5 (2) ◽  
pp. 124
Author(s):  
P. Hemanthkumar ◽  
Y. Sai Kiran ◽  
V. Nava Teja
Keyword(s):  
Performance Metrics ◽  
Finite Impulse Response ◽  
Vlsi Design ◽  
Fir Filter ◽  
Inner Product ◽  
Distributed Arithmetic ◽  
Power Efficient ◽  
Consumption Energy ◽  
The Look ◽  
Suitable Area

<p>Here, we exhibit the design optimization of one- and two-dimensional fully-pipelined computing structures for area-delay-power-efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-based inner-product computation. This plan is found to offer a flexible choice of the address length of the look-up-tables (LUT) for DA-based computation to determine suitable area-time trade-off. It is seen that by using smaller address-lengths for DA-based computing units, it is possible to decrease the memory-size but on the other side that leads to increase of adder complexity and the latency. For efficient DA-based realization of FIR filters of different orders, the flexible linear systolic design is implemented on a Xilinx Virtex-E XCV2000E FPGA using a hybrid combination of Handel-C and parameterizable VHDL cores. Various key performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, energy density and energy throughput are estimated for different filter orders and address-lengths. Obtained results on analysis shows that performance metrics of the proposed implementation is broadly in line with theoretical expectations. We have seen that the choice of address-length M=4 gives the best of area-delay power-efficient realizations of the FIR filter for different filter orders. Moreover, the proposed FPGA implementation is found to involve significantly less area-delay complexity compared with the existing DA-based implementations of FIR filter.</p>

An Efficient High-Throughput Generic QAM Transmitter with Scalable Spiral FIR Filter

2018 ◽  
Vol 28 (01) ◽  
pp. 1950015 ◽  
Author(s):  
Shalina Percy Delicia Figuli ◽  
Jürgen Becker
Keyword(s):  
High Speed ◽  
Forward Error Correction ◽  
Finite Impulse Response ◽  
State Of The Art ◽  
Fir Filter ◽  
The State ◽  
Maximum Throughput ◽  
Digital Implementation ◽  
Filter Length ◽  
Correction Technique

The need for efficient Finite Impulse Response (FIR) filters in high-speed applications such as telecommunications targets Field Programmable Gate Arrays (FPGAs) as an effective and flexible platform for digital implementation. Although FIR filter offers many advantages, its convolution nature poises a challenge in parallelization due to data dependency and computational complexity. To resolve this, we propose a novel FPGA-based reconfigurable filter architecture, which processes several data samples in parallel and breaks down data interdependency in a spiral fashion. Experimental results show a throughput of 7.2[Formula: see text]GSPS with an operating frequency of only 450[Formula: see text]MHz for a filter length of 11 with 16 parallel inputs. With parallelization of 4, it is 4.44 times faster than the state-of-the-art solution for a filter length of 16 and a promising 1.04[Formula: see text]GSPS throughput is achieved for a higher order of length 61. Incorporated into a generic Quadrature Amplitude Modulation (QAM) transmitter fitted with Forward Error Correction technique, a maximum throughput of 23[Formula: see text]Gb/s is achieved by the system for processing 16 input samples in parallel. In comparison to the state-of-the-art mixed domain approach, a threefold performance gain, while utilizing comparatively less Look-up Tables (LUTs), registers and DSP48 slices with an average gain factor of 43.3[Formula: see text], 4.7[Formula: see text] and 3.9[Formula: see text], respectively, is accomplished.

scholarly journals HIGH PERFORMANCE ADAPTIVE FINITE IMPULSE RESPONSE FILTER USING NEW DISTRIBUTED ARITHMETIC ALGORITHM

2017 ◽  
Vol 10 (13) ◽  
pp. 352
Author(s):  
Sandeep Kumar ◽  
Vigneswaran T
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Power Filter ◽  
Arithmetic Algorithm

Finite Impulse Response (FIR) filters is very important in signal Processing Applications. This research is to analyze the performance of FIR filter with the Xilinx Software. The Distributed Arithmetic (DA) algorithm is extensively used in FIR Filter to improve its speed and reducing the area of the filter. The design of low power filter will be achieved by pipelining and parallel processing concept on distributed Arithmetic. The aim is to design filter which has less delay time and supports the pipelining/parallel processing feature, helps in high speed with less power dissipation and area. The paper discusses FPGA implementation of FIR filter and due to parallel data processing its computation is fast and also provides an efficient architecture in terms of area and power consumption. New Distributed   Arithmetic is a high performance and for low power filter.

scholarly journals FPGA Implementation of high speed-low energy RNS based Reconfigurable-FIR Filter for Cognitive Radio Applications

2021 ◽  
Vol 16 ◽  
pp. 278-293
Author(s):  
C. Srinivasa Murthy ◽  
K. Sridevi
Keyword(s):  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Data Partitioning ◽  
Input Word ◽  
Trade Off ◽  
Filter Length ◽  
Reverse Conversion ◽  
Residue Number

The Finite impulse response (FIR) filter is prominently employed in many digital signal processing (DSP) systems for various applications. In this paper, we present a high-performance RNS based FIR filter design for filtration in SDR applications. In general, the residue number system (RNS) gives significant metrics over FIR implementation with its inherent parallelism and data partitioning mechanism. But with increased bit width cause considerable performance trade-off due to both residue computation and reverse conversion. In this paper optimized Residue Number System (RNS) arithmetic is proposed which includes distributed arithmetic based residue computation during RNS multiplication followed by speculative delay optimized reverse computation to mitigate the FIR filter trade-off characteristics with filter length. The proposed RNS design utilizes built-in RAMs block present in the devices of FPGA to accomplish the process of reverse conversion and to store pre-computational values. A distinctive feature of the proposed FIR filter implementation with core optimized RNS is to minimize hardware complexity overhead with the improved operating speed. Initially, fetal audio signal detection is carried out to validate the functionality of FIR filter core and FPGA hardware synthesis is carried out for various input word size and FIR length. From the experimental, it is proved that the trade-off exists in conventional RNS FIR over filter length is narrow down along with considerable complexity reduction with our proposed optimized RNS system.

scholarly journals Design of parallel and pipelined DA based OBC fir filter for software defined radio

2019 ◽  
Vol 14 (3) ◽  
pp. 1228
Author(s):  
Rajmohan Madasamy ◽  
Himanshu Shekhar
Keyword(s):  
Software Defined Radio ◽  
Finite Impulse Response ◽  
New Technology ◽  
Intermediate Frequency ◽  
Fir Filter ◽  
Inner Product ◽  
Distributed Arithmetic ◽  
Binary Coding ◽  
Processing Block ◽  
Address Line

Software Defined Radio (SDR) is a new technology used to implement different wireless communication standard for mobile communication. The Intermediate Frequency (IF) block is the most demanding block in software defined radio. The most important task in intermediate processing block is digital filtering which is carried out by Finite Impulse Response (FIR) filter. One of the major techniques for the calculation of inner product is Distributed Arithmetic (DA) based FIR filter which uses Look Up Table (LUT) to eliminate the need of multiplier. The efficiency of the DA filter is affected with the increasing number of address line and also due to its serial operation. To overcome this problem parallel and pipeline based DA filter using Offset Binary Coding (OBC) for Two Bit At A Time (2-BAAT) is proposed. Our proposed method achieves less area, low power consumption and nominal delay for SDR application.

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