scholarly journals High Speed Area Efficient FPGA Implementation of AES Algorithm

2018 ◽  
Vol 7 (3) ◽  
pp. 151
Author(s):  
P. B. Mane ◽  
A. O. Mulani
Keyword(s):  
Power Consumption ◽  
High Throughput ◽  
High Speed ◽  
Advanced Encryption Standard ◽  
Digital Information ◽  
Unauthorized Access ◽  
Aes Algorithm ◽  
Symmetric Key ◽  
Reconfigurable Platform ◽  
Symmetric Key Cryptography

Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.

scholarly journals High Speed Area Efficient FPGA Implementation of AES Algorithm

2018 ◽  
Vol 7 (3) ◽  
pp. 157
Author(s):  
P. B. Mane ◽  
A. O. Mulani
Keyword(s):  
Power Consumption ◽  
High Throughput ◽  
High Speed ◽  
Advanced Encryption Standard ◽  
Digital Information ◽  
Unauthorized Access ◽  
Aes Algorithm ◽  
Symmetric Key ◽  
Reconfigurable Platform ◽  
Symmetric Key Cryptography

Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.

scholarly journals Advanced Encryption Standard for Data Encryption using EDK Environment in FPGA

2019 ◽  
Vol 8 (4) ◽  
pp. 11969-11972
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Data Encryption ◽  
Advanced Encryption Standard ◽  
Gate Arrays ◽  
Aes Algorithm ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Efficient Processing

now a day’s VLSI is developing technology as predicted by Moors law which is drastically increasing as per demand one of that is data security for efficient processing so, data encryption and decryption are major play in security for this an advanced encryption standard is there which uses reconfigurable hardware process in this paper field programmable gate arrays (FPGAs) kit of Xilinx based platform in which spartan3E EDK kit is used. Here we analyze the speed of AES algorithm by using this EDK environment where obvious high speed is considerable and with power consumption and throughput exemptions. With micro blaze soft core processer we implement our algorithm of AES by using c coding we configure the hardware structure. EDK tool with one round operation is done and both area utilization and throughput are observed as we are familiar that when area reduces power consumption also reduces.

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

scholarly journals RK Algorithm: Stochastic Parallel Methodology for Symmetric Key Cryptography

2017 ◽  
Vol 2 (3) ◽  
pp. 137-144
Author(s):  
Yegireddi Ramesh ◽  
Kiran Kumar Reddi
Keyword(s):  
Information Age ◽  
Block Size ◽  
Large Data ◽  
Digital Information ◽  
Text Data ◽  
Plain Text ◽  
Cipher Text ◽  
Wide Range ◽  
Symmetric Key ◽  
Symmetric Key Cryptography

With the enormous growth in the Internet and network, data security has become an inevitable concern for any organization. From antecedent security has attracted considerable attention from network researchers. In this perspective many possible fields of endeavour come to mind with many cryptographic algorithms in a broader way, each is highly worthy and lengthy. As society is moving towards digital information age we necessitate highly standard algorithms which compute faster when data size is of wide range or scope. On survey, numerous sequential approaches carried out by symmetric key algorithms on 128 bits as block size are ascertained to be highly in securable and resulting at a low speed. As in the course the commodities are immensely parallelized on multi core processors to solve computational problems, in accordance with, propound parallel symmetric key based algorithms to encrypt/decrypt large data for secure conveyance. The algorithm is aimed to prevail by considering 64 character (512 bits) plain text data, processed 16 characters separately by applying parallelism and finally combine each 16 character cipher data to form 64 character cipher text. The round function employed in the algorithm is very complex, on which improves efficacy.

CompactRIO Based Real Time Implementation of AES Algorithm for Embedded Applications

2019 ◽  
Vol 10 (2) ◽  
pp. 19-36
Author(s):  
El Adib Samir ◽  
Raissouni Naoufal
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Software Design ◽  
System Architecture ◽  
Advanced Encryption Standard ◽  
Time Cost ◽  
Security Applications ◽  
Aes Algorithm ◽  
Embedded Applications ◽  
Different Levels

For real-time embedded applications, several factors (time, cost, power) that are moving security considerations from a function-centric perspective into a system architecture (hardware/software) design issue. The National Institute of Standards and Technology (NIST) adopts Advanced Encryption Standard (AES) as the most widely used encryption algorithm in many security applications. The AES algorithm specifies 10, 12 and 14 rounds offering different levels of security. Although the number of rounds determines the strength of security, the power consumption issue has risen recently, especially in real-time embedded systems. In this article, the authors present real time implementation of the AES encryption on the compactRIO platform for a different number of AES rounds. The target hardware is NI cRIO-9022 embedded real-time controller from National Instruments (NI). The real time encryption processing has been verified successfully. The power consumption and encryption time experimental results are presented graphically for 10, 12 and 14 rounds of processing.

scholarly journals Generating Cipher Text using BLOWFISH Algorithm for Secured Data Communications

2019 ◽  
Vol 9 (2) ◽  
pp. 117-121
Keyword(s):  
High Speed ◽  
High Performance ◽  
Encryption Algorithm ◽  
Advanced Encryption Standard ◽  
Aes Algorithm ◽  
Cipher Text ◽  
Original Message ◽  
Public Domain Software ◽  
Secured Data ◽  
Vhdl Code

Cryptography plays a major role in the network security. In order to secure the data one must do encryption of the original message. In this paper, the design and analysis of high speed and high performance BLOWFISH algorithm is implemented in VHDL coding and compared with AES (Advanced Encryption Standard) algorithm. The BLOWFISH algorithm involves the process of giving the data and key as input to the encryption block. BLOWFISH encryption algorithm is designed and programmed in VHDL coding. Then it is implemented in Xilinx 10.1. This research is carried in the following steps: designing of encryption algorithm, writing VHDL code, simulating the code on “ModelSim altera 6.5e”, synthesizing and implementing the code using Xilinx’s ISE 10.1.This research aims in developing flexible and technology independent architectures in the areas of VPN software, file compression, public domain software such as smart cards, etc. Also presents the comparison of BLOWFISH and AES algorithms. Experimental results show that BLOWFISH algorithm runs faster than AES algorithm while both of them consume almost the same Power.

scholarly journals Watermarking and Cryptography Based Image Authentication on Reconfigurable Platform

2017 ◽  
Vol 6 (2) ◽  
pp. 181-187
Author(s):  
Altaf O. Mulani ◽  
P. B. Mane
Keyword(s):  
Complete System ◽  
Digital Rights Management ◽  
Image Authentication ◽  
Digital Data ◽  
Advanced Encryption Standard ◽  
Digital Information ◽  
Digital Rights ◽  
Simulink Model ◽  
Rights Management ◽  
Reconfigurable Platform

Now-a-days, multimedia based applications have been developed rapidly. Digital information is easy to process but it allows illegal users to access the data. For protecting the data from this illegal use, Digital Rights Management (DRM) can be used. DRM allows secure exchange of digital data over internet or other electronic media. In this paper, FPGA based implementation of DWT alongwith Advanced Encryption Standard (AES) based watermarking is discussed. With this approach, improved security can be achieved. The complete system is designed using HDL and simulated using Questasim and MATLAB Simulink model. The synthesis result shows that this implementation occupies only 2117 slices and maximum frequency reported for this design is 228.064 MHz.

scholarly journals Hybrid Approach of Modified AES

Cryptography ◽  
2020 ◽  
pp. 129-141
Author(s):  
Filali Mohamed Amine ◽  
Gafour Abdelkader
Keyword(s):  
Time Complexity ◽  
Input Data ◽  
Hybrid Approach ◽  
Encryption Algorithm ◽  
Advanced Encryption Standard ◽  
Aes Algorithm ◽  
Symmetric Key ◽  
Encryption Algorithms ◽  
Aes Encryption Algorithm ◽  
Modified Aes

Advanced Encryption Standard is one of the most popular symmetric key encryption algorithms to many works, which have employed to implement modified AES. In this paper, the modification that has been proposed on AES algorithm that has been developed to decrease its time complexity on bulky data and increased security will be included using the image as input data. The modification proposed itself including alteration in the mix column and shift rows transformation of AES encryption algorithm, embedding confusion-diffusion. This work has been implemented on the most recent Xilinx Spartan FPGA.

Hybrid Approach of Modified AES

2017 ◽  
Vol 7 (4) ◽  
pp. 83-93
Author(s):  
Filali Mohamed Amine ◽  
Gafour Abdelkader
Keyword(s):  
Time Complexity ◽  
Input Data ◽  
Hybrid Approach ◽  
Encryption Algorithm ◽  
Advanced Encryption Standard ◽  
Aes Algorithm ◽  
Symmetric Key ◽  
Encryption Algorithms ◽  
Aes Encryption Algorithm ◽  
Modified Aes

Advanced Encryption Standard is one of the most popular symmetric key encryption algorithms to many works, which have employed to implement modified AES. In this paper, the modification that has been proposed on AES algorithm that has been developed to decrease its time complexity on bulky data and increased security will be included using the image as input data. The modification proposed itself including alteration in the mix column and shift rows transformation of AES encryption algorithm, embedding confusion-diffusion. This work has been implemented on the most recent Xilinx Spartan FPGA.

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