scholarly journals Implementation of a High-Speed and High-Throughput Advanced Encryption Standard

2022 ◽  
Vol 31 (2) ◽  
pp. 1025-1036
Author(s):  
T. Manoj Kumar ◽  
P. Karthigaikumar
Keyword(s):  
High Throughput ◽  
High Speed ◽  
Advanced Encryption Standard

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

scholarly journals High Speed Area Efficient FPGA Implementation of AES Algorithm

2018 ◽  
Vol 7 (3) ◽  
pp. 151
Author(s):  
P. B. Mane ◽  
A. O. Mulani
Keyword(s):  
Power Consumption ◽  
High Throughput ◽  
High Speed ◽  
Advanced Encryption Standard ◽  
Digital Information ◽  
Unauthorized Access ◽  
Aes Algorithm ◽  
Symmetric Key ◽  
Reconfigurable Platform ◽  
Symmetric Key Cryptography

Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.

scholarly journals High Speed Area Efficient FPGA Implementation of AES Algorithm

2018 ◽  
Vol 7 (3) ◽  
pp. 157
Author(s):  
P. B. Mane ◽  
A. O. Mulani
Keyword(s):  
Power Consumption ◽  
High Throughput ◽  
High Speed ◽  
Advanced Encryption Standard ◽  
Digital Information ◽  
Unauthorized Access ◽  
Aes Algorithm ◽  
Symmetric Key ◽  
Reconfigurable Platform ◽  
Symmetric Key Cryptography

Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.

scholarly journals Fully Automated Cultivation of Adipose-Derived Stem Cells in the StemCellDiscovery—A Robotic Laboratory for Small-Scale, High-Throughput Cell Production Including Deep Learning-Based Confluence Estimation

Processes ◽  
2021 ◽  
Vol 9 (4) ◽  
pp. 575
Author(s):  
Jelena Ochs ◽  
Ferdinand Biermann ◽  
Tobias Piotrowski ◽  
Frederik Erkens ◽  
Bastian Nießing ◽  
...  
Keyword(s):  
Stem Cells ◽  
Deep Learning ◽  
High Throughput ◽  
High Speed ◽  
New Technologies ◽  
Human Mesenchymal Stem Cells ◽  
Simulation Software ◽  
System Capacity ◽  
Small Scale ◽  
Production Environment

Laboratory automation is a key driver in biotechnology and an enabler for powerful new technologies and applications. In particular, in the field of personalized therapies, automation in research and production is a prerequisite for achieving cost efficiency and broad availability of tailored treatments. For this reason, we present the StemCellDiscovery, a fully automated robotic laboratory for the cultivation of human mesenchymal stem cells (hMSCs) in small scale and in parallel. While the system can handle different kinds of adherent cells, here, we focus on the cultivation of adipose-derived hMSCs. The StemCellDiscovery provides an in-line visual quality control for automated confluence estimation, which is realized by combining high-speed microscopy with deep learning-based image processing. We demonstrate the feasibility of the algorithm to detect hMSCs in culture at different densities and calculate confluences based on the resulting image. Furthermore, we show that the StemCellDiscovery is capable of expanding adipose-derived hMSCs in a fully automated manner using the confluence estimation algorithm. In order to estimate the system capacity under high-throughput conditions, we modeled the production environment in a simulation software. The simulations of the production process indicate that the robotic laboratory is capable of handling more than 95 cell culture plates per day.

High-speed and high-precision fluorescence-based cell count and viability assays using the Cellaca™ MX high-throughput cell counter

Cytotherapy ◽  
2021 ◽  
Vol 23 (5) ◽  
pp. S97
Author(s):  
J. Bell ◽  
Y. Huang ◽  
S. Yung ◽  
H. Qazi ◽  
C. Hernandez ◽  
...  
Keyword(s):  
Cell Count ◽  
High Precision ◽  
High Throughput ◽  
High Speed ◽  
Cell Counter

Enhanced Air-Gap Control for High-Speed Plasmonic Lithography Using Solid Immersion Lens With Sharp-Ridge Nanoaperture

2011 ◽  
Author(s):  
Hyunwoo Hwang ◽  
Won-Sup Lee ◽  
No-Cheol Park ◽  
Hyunseok Yang ◽  
Young-Pil Park ◽  
...  
Keyword(s):  
Surface Plasmon Resonance ◽  
Surface Plasmon ◽  
High Throughput ◽  
High Speed ◽  
Low Cost ◽  
Near Field ◽  
Nanometer Scale ◽  
Field Region ◽  
High Speeds ◽  
Gap Control

Recently, plasmonic nanolithography is studied by many researchers (1, 2 and 3). This presented a low-cost and high-throughput approach to maskless nanolithography technique that uses a metallic sharp-ridge nanoaperture with a high strong nanometer-sized optical spot induced by surface plasmon resonance. However, these nanometer-scale spots generated by metallic nanoapertures are formed in only the near-field region, which makes it very difficult to pattern above the photoresist surface at high-speeds.

scholarly journals High Throughput Error Control Using Parallel CRC

VLSI Design ◽  
1994 ◽  
Vol 2 (1) ◽  
pp. 33-50
Author(s):  
Andrzej Sobski ◽  
Alexander Albicki
Keyword(s):  
High Throughput ◽  
High Speed ◽  
Error Control ◽  
Cyclic Codes ◽  
Shift Register ◽  
Linear Feedback ◽  
Clock Period ◽  
Feedback Shift Register ◽  
Parallel Stream ◽  
Speed Computer

Redesigning the LFSR (Linear Feedback Shift Register) so that syndrome calculations can be performed in one sweep allows for fast error control in high speed computer networks. The resulting structure forms the basis of the PEDDC (Parallel Encoder, Decoder, Detector, Corrector) which replaces the conventional Serial Encoder, Decoder, Detector, Corrector for generation and utilization of cyclic codes. Since syndromes are calculated in as little as one clock period, information from which the syndrome is calculated can be processed in a parallel stream. In this paper a simple PEDDC is built, its operation is examined in detail, its performance is compared with a serial counterpart, possible variations on the PEDDC structure is given, and further speed enhancement techniques are considered.

High-Throughput DNA Plasmid Transfection Using Acoustic Droplet Ejection Technology

2018 ◽  
Vol 24 (4) ◽  
pp. 492-500
Author(s):  
Béatrice Colin ◽  
Benoit Deprez ◽  
Cyril Couturier
Keyword(s):  
High Throughput ◽  
Plasmid Dna ◽  
High Speed ◽  
Protein Crystallization ◽  
Dna Transfection ◽  
Dna Amount ◽  
Biological Assays ◽  
Droplet Ejection ◽  
Plasmid Transfection ◽  
Automated Protocol

The Labcyte Echo acoustic liquid handler allows accurate droplet ejection at high speed from a source well plate to a destination plate. It has already been used in various miniaturized biological assays, such as quantitative PCR (q-PCR), quantitative real-time PCR (q-RT-PCR), protein crystallization, drug screening, cell dispensing, and siRNA transfection. However, no plasmid DNA transfection assay has been published so far using this dispensing technology. In this study, we evaluated the ability of the Echo 550 device to perform plasmid DNA transfection in 384-well plates. Due to the high throughput of this device, we simultaneously optimized the three main parameters of a transfection process: dilution of the transfection reagent, DNA amount, and starting DNA concentration. We defined a four-step protocol whose optimal settings allowed us to transfect HeLa cells with up to 90% efficiency and reach a co-expression of nearly 100% within transfected cells in co-transfection experiments. This fast, reliable, and automated protocol opens new ways to easily and rapidly identify optimal transfection settings for a given cell type. Furthermore, it permits easy software-based transfection control and multiplexing of plasmids distributed on wells of a source plate. This new development could lead to new array applications, such as human ORFeome protein expression or CRISPR-Cas9-based gene function validation in nonpooled screening strategies.

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