Two state-of-the-arts current-mode ternary full adders based on  CNTFET Technology

Adder core respecting to its various applications in VLSI circuits and systems is considered as the most critical building block in microprocessors, digital signal processors and arithmetic operations. Novel designs of a low power and complexity Current Mode 1-bit Full Adder cell based on CNTFET technology has been presented in this paper. Three major parts construct their structures; 1) the first part that converts current to voltage; 2) threshold detectors (TD); and 3) parallel paths to convey the output currents flow. Adjusting threshold voltages which are significant factor for setting threshold detectors switching point has been achieved by means of CNTFET technology. It would bring significant improvements in adjusting threshold voltages, regarding to its unique characterizations. Simple design, less transistor counts and static power dissipation and better performance comparing previous designs could be considered as some advantages of the novel designs.

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Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

International Journal for Research in Applied Science and Engineering Technology ◽

10.22214/ijraset.2021.37924 ◽

2021 ◽

Vol 9 (9) ◽

pp. 66-70

Author(s):

Nakul C. Kubsad

Keyword(s):

Power Dissipation ◽

High Speed ◽

Digital Signal ◽

Full Adder ◽

Digital Signal Processors ◽

Transmission Gate ◽

Logical Operations ◽

Recent Advancement ◽

Voltage Swing ◽

Signal Processors

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

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Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor

Engineering, Technology & Applied Science Research ◽

10.48084/etasr.3156 ◽

2019 ◽

Vol 9 (6) ◽

pp. 4933-4936

Author(s):

H. Ghabri ◽

D. Ben Issa ◽

H. Samet

Keyword(s):

Performance Optimization ◽

Field Effect Transistor ◽

Digital Circuits ◽

Digital Signal ◽

Full Adder ◽

Cmos Technology ◽

Digital Signal Processors ◽

Effect Transistor ◽

Power Delay Product ◽

Signal Processors

The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

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Implementation of 16 Bit SAR ADC in CMOS and sub threshold cml techniques

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.12.11298 ◽

2018 ◽

Vol 7 (2.12) ◽

pp. 257

Author(s):

K A. Jyotsna ◽

P Satish Kumar ◽

B K. Madhavi ◽

I Swaroopa

Keyword(s):

Low Power ◽

Digital Signal ◽

Current Mode ◽

Threshold Current ◽

Sar Adc ◽

Ultra Low Power ◽

Analog To Digital ◽

Threshold Voltages ◽

Vlsi Technology ◽

Static Power

The trends of the VLSI technology is advancing, due to this majority of the industry players are showing interest in development of the devices with ultra low power applications. Analog-to-Digital converters are getting extensively used in Medical implant machines and in lots of Sensor machines, because it is serving an imperative role in interfacing between analog signal and digital signal. This paper presents a modernistic technique called as Sub threshold Current Mode Logic (CML) for ultra low power digital components. Here 16 bit SAR ADC is designed and compared with the techniques like CMOS and STCML for power consumption and delay. Schematics are materialized with Cadence Virtuoso tool using 45nm process. The transistors in these CML and CMOS operate at threshold voltages and Sub-threshold voltages where the executable design is done using 1V to 0.5V power supply (VDD). The comparator dissipates aggrandized power, so most of the intension is converged on forming this chunk. The CML logic procedure operates primarily with the current domain, due to this the performance can be constitutionally high. This approach decreases static power dissipation.

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