scholarly journals Design of High-Performance 1-Bit Full Adder Cells Based on MOS-Type GNRFETs

2020 ◽  
Vol 6 (1) ◽  
pp. 1
Author(s):  
Alireza Dehghan
Keyword(s):  
High Performance ◽  
Full Adder

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

scholarly journals High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

2021 ◽  
pp. 263-269
Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa
Keyword(s):  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Power Performance ◽  
High Speed Design ◽  
Power Delay Product ◽  
Full Swing ◽  
Output Swing ◽  
High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

High-Performance and Low-Energy Approximate Full Adder Design for Error-Resilient Image Processing

2021 ◽  
Author(s):  
Seyed Hossein Shahrokhi ◽  
Mehdi Hosseinzadeh ◽  
Midia Reshadi ◽  
Saeid Gorgin
Keyword(s):  
Image Processing ◽  
High Performance ◽  
Full Adder ◽  
Low Energy ◽  
Error Resilient

scholarly journals High-performance full adder architecture in quantum-dot cellular automata

2017 ◽  
Vol 2017 (7) ◽  
pp. 394-402 ◽  
Author(s):  
Hamid Rashidi ◽  
Abdalhossein Rezai
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Full Adder ◽  
Quantum Dot Cellular Automata

Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell

2008 ◽  
Vol 3 (2) ◽  
Author(s):  
Keivan Navi ◽  
Omid Kavehei ◽  
Mahnoush Rouholamini ◽  
Amir Sahafi ◽  
Shima Mehrabi ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Full Adder

A novel high-performance and reliable multi-threshold CNFET full adder cell design

2017 ◽  
Vol 7 (1) ◽  
pp. 15 ◽  
Author(s):  
Yavar Safaei Mehrabani ◽  
Mohammad Hossein Shafiabadi
Keyword(s):  
High Performance ◽  
Full Adder ◽  
Cell Design

A NEW ROBUST AND HIGH-PERFORMANCE HYBRID FULL ADDER CELL

2011 ◽  
Vol 20 (04) ◽  
pp. 641-655 ◽  
Author(s):  
REZA FAGHIH MIRZAEE ◽  
MOHAMMAD HOSSEIN MOAIYERI ◽  
HAMID KHORSAND ◽  
KEIVAN NAVI
Keyword(s):  
Power Consumption ◽  
Great Improvement ◽  
High Performance ◽  
Full Adder ◽  
Good Choice ◽  
Lower Power ◽  
Pvt Variations ◽  
Power Delay Product ◽  
Full Swing ◽  
Hspice Simulation

A new 1-bit hybrid Full Adder cell is presented in this paper with the aim of reaching a robust and high-performance adder structure. While most of recent Full Adders are proposed with the purpose of using fewer transistors, they suffer from some disadvantages such as output or internal non-full-swing nodes and poor driving capability. Considering these drawbacks, they might not be a good choice to operate in a practical environment. Lowering the number of transistors can inherently lead to smaller occupied area, higher speed and lower power consumption. However, other parameters, such as robustness to PVT variations and rail-to-rail operation, should also be considered. While the robustness is taken into account, HSPICE simulation demonstrates a great improvement in terms of speed and power-delay product (PDP).

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