New Analytical Drain Current Model for the Sub-Linear Region of Output Characteristics of Graphene Field-Effect Transistors in the Low Carrier Density Limit

2014 ◽  
Vol 14 (12) ◽  
pp. 9082-9087
Author(s):  
Dongheon Lee ◽  
Kihwan Lee ◽  
Kangmin Kim ◽  
Ohyun Kim
2019 ◽  
Vol 86 (3) ◽  
pp. 30101
Author(s):  
Xiang-Jie Xiao ◽  
Piao-Rong Xu ◽  
Gen-Hua Liu ◽  
Hui-Ying Zhou ◽  
Jian-Jun Li ◽  
...  

A numerical model of carrier saturation velocity and drain current for the monolayer graphene field effect transistors (GFETs) is proposed by considering the exponential distribution of potential fluctuations in disordered graphene system. The carrier saturation velocity of GFET is investigated by the two-region model, and it is found to be affected not only by the carrier density, but also by the graphene disorder. The numerical solutions of the carrier density and carrier saturation velocity in the disordered GFETs yield clear and physical-based results. The simulated results of the drain current model show good consistency with the reported experimental data.


2019 ◽  
Vol 58 (9) ◽  
pp. 095001
Author(s):  
Jiarui Bao ◽  
Shuyan Hu ◽  
Guangxi Hu ◽  
Laigui Hu ◽  
Ran Liu ◽  
...  

2013 ◽  
Vol 89 ◽  
pp. 134-138 ◽  
Author(s):  
Ashkhen Yesayan ◽  
Fabien Prégaldiny ◽  
Jean-Michel Sallese

2013 ◽  
Vol 60 (2) ◽  
pp. 848-855 ◽  
Author(s):  
Juan Pablo Duarte ◽  
Sung-Jin Choi ◽  
Dong-Il Moon ◽  
Jae-Hyuk Ahn ◽  
Jee-Yeon Kim ◽  
...  

Nanomaterials ◽  
2019 ◽  
Vol 9 (2) ◽  
pp. 181 ◽  
Author(s):  
Hongliang Lu ◽  
Bin Lu ◽  
Yuming Zhang ◽  
Yimen Zhang ◽  
Zhijun Lv

The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.


AIP Advances ◽  
2019 ◽  
Vol 9 (2) ◽  
pp. 025222 ◽  
Author(s):  
Feng Zhuang ◽  
Wanling Deng ◽  
Xiaoyu Ma ◽  
Junkai Huang

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