A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part II: Drain Current Model

2013 ◽  
Vol 60 (2) ◽  
pp. 848-855 ◽  
Author(s):  
Juan Pablo Duarte ◽  
Sung-Jin Choi ◽  
Dong-Il Moon ◽  
Jae-Hyuk Ahn ◽  
Jee-Yeon Kim ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Current Model ◽  
Drain Current ◽  
Core Model

An analytical drain current model for graphene nanoribbon tunnel field-effect transistors

2019 ◽  
Vol 58 (9) ◽  
pp. 095001
Author(s):  
Jiarui Bao ◽  
Shuyan Hu ◽  
Guangxi Hu ◽  
Laigui Hu ◽  
Ran Liu ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Current Model ◽  
Drain Current ◽  
Graphene Nanoribbon

Explicit drain current model of junctionless double-gate field-effect transistors

2013 ◽  
Vol 89 ◽  
pp. 134-138 ◽  
Author(s):  
Ashkhen Yesayan ◽  
Fabien Prégaldiny ◽  
Jean-Michel Sallese
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Current Model ◽  
Drain Current ◽  
Double Gate

scholarly journals Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Nanomaterials ◽  
2019 ◽  
Vol 9 (2) ◽  
pp. 181 ◽  
Author(s):  
Hongliang Lu ◽  
Bin Lu ◽  
Yuming Zhang ◽  
Yimen Zhang ◽  
Zhijun Lv
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Current Model ◽  
Tunneling Current ◽  
Drain Current ◽  
Device Structure ◽  
Band Engineering ◽  
Novel Device ◽  
Analytical Potential ◽  
Good Agreement

The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.

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