Ψηφιακή σχεδίαση και υλοποίηση κάρτας κρυπτογράφησης για μυστική επικοινωνία βασισμένη σε FPGA τεχνολογία

2009 ◽  
Author(s):  
Παναγιώτης Μαργαρώνης
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Linear Feedback ◽  
Description Language ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Hardware Description ◽  
Feedback Shift Register ◽  
Very High

Η παρούσα διατριβή παρουσιάζει τη διαδικασία σχεδίασης και υλοποίησης μιας ολοκληρωμένης και αυτόνομης κάρτας κρυπτογράφησης. Η συγκεκριμένη κάρτα έχει ονομαστεί LAM και εισάγει ένα ψηφιακό ολοκληρωμένο κύκλωμα το οποίο βασίζεται στο Peripheral Component Interconnection (PCI) δίαυλο. Η υλοποίηση της παραπάνω κάρτας κρυπτογράφησης σχεδιάστηκε με τη χρήση προγραμματιζόμενου ολοκληρωμένου κυκλώματος Field Programmable Gate Arrays (FPGA). Ο αντικειμενικός σκοπός της διατριβής είναι να προσφέρει σε βάθος γνώση αναφορικά με τη διαδικασία σχεδίασης και υλοποίησης ενός ψηφιακού κυκλώματος κρυπτογράφησης που βασίζεται στην τεχνολογία των ολοκληρωμένων προγραμματιζόμενων κυκλωμάτων FPGA με χρήση της γλώσσας περιγραφής υλικού Very High Speed Integrated Circuits Hardware Description Language (VHDL). Το συγκεκριμένο ψηφιακό κύκλωμα μπορεί να αξιοποιηθεί σαν κάρτα προσωπικού υπολογιστή. Η προαναφερόμενη κάρτα σχεδιάστηκε και υλοποιήθηκε σαν μια ολοκληρωμένη διαφανής συσκευή με δυνατότητα συμμετρικής κρυπτογράφησης/αποκρυπτογράφησης, ενσωματώνοντας ένα σύστημα δημιουργίας και διαχείρισης κλειδιών κρυπτογράφησης καθώς και συγχρονισμού με άλλες επικοινωνούντες συσκευές. Για την εκπόνηση της διατριβής πραγματοποιήθηκε μελέτη στα παρακάτω ερευνητικά πεδία. Στο πρώτο στάδιο μελετήθηκαν τα κυκλώματα FPGA, η γλώσσα περιγραφής υλικού VHDL, η κατανομή και ο χώρος σχεδίασης που περιλαμβάνει η υλοποίηση του κυκλώματος εσωτερικά στο Chip και τα εργαλεία υλοποίησης και ανάπτυξης. Στο δεύτερο στάδιο έγινε μελέτη των αρχών μετάδοσης δεδομένων μέσω του Internet, της κάρτας διασύνδεσης Ethernet και της επικοινωνίας πραγματικού χρόνου μέσω TCP/IP πρωτοκόλλου. Στο τρίτο στάδιο πραγματοποιήθηκε μελέτη στο μετασχηματισμό και μεταφορά κλειδιών από εξωτερική μνήμη στην εσωτερική μνήμη της κάρτας κρυπτογράφησης με τη βοήθεια Linear Feedback Shift Register (LFSR), στον προγραμματισμό LFSR και στην επιλογή κλειδιών (αδύναμα κλειδιά). Στο τέταρτο στάδιο μελετήθηκαν ερευνητικά θέματα που άπτονται της δημιουργίας και διαχείρισης κλειδιών συμμετρικής κρυπτογραφίας. Έπειτα έγινε μελέτη στη μετάδοση ψηφιακών δεδομένων μέσω πρωτοκόλλων DVB/DAB. Στη συνέχεια μελετήθηκε η εξουσιοδότηση χρήστη με Έξυπνες Κάρτες (Smart Cards) και το πρωτόκολλο ανάγνωσης των έξυπνων καρτών. Επιπλέον μελετήθηκαν η αρχιτεκτονική, οι αρχές επικοινωνίας του PCI διαύλου και ο χρονισμός του συστήματος, ενώ έγινε και ανάλυση των υπαρχόντων συμμετρικών αλγορίθμων κρυπτογράφησης που έχουν υλοποιηθεί σε επίπεδο υλικού. Ένα ακόμη πεδίο μελέτης υπήρξε ο συγχρονισμός των καρτών κρυπτογράφησης σε απομακρυσμένα συστήματα καθώς και η διάρκεια της ασφαλούς επικοινωνίας. Τέλος μελετήθηκαν οι βασικές αρχές για την προστασία από εξωτερικές παρεμβολές λόγω ηλεκτρομαγνητικής ακτινοβολίας καθώς και οι απαιτήσεις από εξωτερικά κυκλώματα για την ικανοποίηση των ηλεκτρικών απαιτήσεων της κάρτας.

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

FPGA Implementation of a Novel Construction of Optical Zero-Correlation Zone Codes for OCDMA Systems

2019 ◽  
Vol 0 (0) ◽  
Author(s):  
Samia Driz ◽  
Benattou Fassi ◽  
Mohammed Amine Mansour ◽  
Abdelmalik Taleb-Ahmed
Keyword(s):  
Code Division Multiple Access ◽  
Description Language ◽  
Gate Arrays ◽  
Zero Correlation ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Novel Method ◽  
Zero Correlation Zone ◽  
Code Division Multiple ◽  
Very High

AbstractThis paper proposes a novel method for constructing optical zero-correlation zone (OZCZ) codes based on the Mutually Orthogonal Complementary Sets (MOCS) matrix and the concatenation operation. The most important property of the obtained codes is that the periodic correlation function of the proposed codes is zero for the phase shifts within the zero-correlation zone. The procedure of construction is simple, flexible and offers increasing number of users \left( {M = {2^{n + 1}}} \right). In the other hand, we have presented a fully reconfigurable hardware implementation based on very high description language of the proposed OZCZ codes for optical code-division multiple-access encoder system. The implementation is performed on an Altera field-programmable gate arrays device using ROM memory and an up counter. The simulation results have been found satisfactory and are in conformity with the theoretical observations.

FPGA-BASED MOTION CONTROLLER FOR WAFER-HANDLING ROBOT

2013 ◽  
Vol 37 (3) ◽  
pp. 427-437
Author(s):  
Hsin-Hung Chou ◽  
Ying-Shieh Kung ◽  
Tai-Wei Tsui ◽  
Stone Cheng
Keyword(s):  
Hardware Description Language ◽  
Motion Controller ◽  
Description Language ◽  
Gate Arrays ◽  
Current Vector ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Axis Position ◽  
Hardware Description ◽  
Fpga Chip

This study applies FPGA (Field Programmable Gate Arrays) technology to implement a motion controller for wafer-handling robot which has three-DOF (Degree of Freedom) motion. The proposed FPGA-based motion controller has two modules. The first module is Nios II processor which is used to realize the motion trajectory computation and the three-axis position/speed controllers. The second module is demonstrated to implement the three-axis current vector controllers by using FPGA hardware, and VHDL (VHSIC Hardware Description Language) is adopted to describe the controller behavior. Therefore, a fully digital motion controller for wafer-handling robot, such as one trajectory planning, three current vector controllers and three position/speed controllers are all implemented with an FPGA chip.

FPGA-Realization of Vector Control for PMSM Drives

2013 ◽  
Vol 311 ◽  
pp. 249-254
Author(s):  
Nguyen Vu Quynh ◽  
Ying Shieh Kung ◽  
Pham Van Dung ◽  
Kuan Yuen Liao ◽  
Sheng Wei Chen
Keyword(s):  
Vector Control ◽  
High Speed ◽  
Pulse Width Modulation ◽  
Control Method ◽  
Experimental System ◽  
Control Algorithms ◽  
Description Language ◽  
Field Programmable ◽  
Hardware Description ◽  
Very High

The design and implementation of a vector control for Permanent Magnetic Synchronous Motor (PMSM) based on Field Programmable Gate Array (FPGA) technology is presented in this paper. Firstly, a Space Vector Pulse Width Modulation (SVPWM) scheme, vector control method and PI controller are derived. Secondly, the Very-High-Speed IC Hardware Description Language (VHDL) is adopted to describe the behavior of the aforementioned control algorithms. Finally, an experimental system is setup to evaluate the effectiveness and correctness of the proposed vector controller for PMSM drives.

scholarly journals Support Vector Machine working on FPGA and the segmentation method of brain MR screening

2017 ◽  
Vol 4 (3) ◽  
pp. 120 ◽  
Author(s):  
Fatih Şişik ◽  
Eser Sert
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Support Vector ◽  
Segmentation Method ◽  
Description Language ◽  
Field Programmable ◽  
Hardware Description ◽  
Very High

Alan Programlanabilir Kapı Dizileri (Field Programmable Gate Array-FPGA) programlanabilir sayısal bloklar ve bağlantılarını içeren cihazlar olup çok esnek ve hızlı çalışabilme özelliklerine sahiptir. Programlanabilen bu sayısal kapılar sayesinde karmaşık tasarımlar kolay bir şekilde geliştirilebilmektedir. FPGA’lar küçük boyutlarda olup bilgisayardan bağımsız mobil olarak ve bilgisayarlardan daha yüksek hızlarda çalışabilmektedirler. Veri madenciliğinin görevlerinden biri olan sınıflandırma probleminin çözümü için geliştirilmiş önemli makine öğrenimi algoritmalarından biri Destek Vektör Makineleri’ dir. Literatürde Destek Vektör Makineleri’ nin diğer birçok tekniğe göre daha başarılı sonuçlar verdiği kanıtlanmıştır. Tümör analizi, yüz tanıma, robotik göz oluşturma gibi konular, araştırmacıların görüntü işleme alanında yoğun olarak üzerinde çalıştıkları güncel, önemli ve zor problemlerden bazılarıdır. Bilgisayarda yapılan tümör analizinde, grafik ve resimlerin işlenmesinde yavaş işlem yapma ve aynı zamanda mobil olmama sorunlarından, FPGA donanımı ile görüntü işlemede bu sorunların üstesinden gelinmektedir. Bu çalışmada FPGA donanımında çalışan destek vektör makinası kullanılarak daha gerçekçi tümör analizi yapılarak tümörlü bölgelerin bulunması ve gerekli analiz sonuçlarının gösterilmesi amaçlanmaktadır. Böylece sağlık alanında da kullanılabilecek yararlı bir donanımın tasarımı gerçekleştirilecektir. Dolayısıyla gömülü sistemlerle anlatılan bu işlem süreçlerini gerçekleştiren çalışma sayısı çok az olduğundan çalışma özgün değer taşımaktadır. Buna ek olarak, FPGA’ ya özgü donanım tanımlama dillerinden biri olan Çok Yüksek Hızlı Tümleşik Devre Tanımlama Dili (Very High Speed Integrated Circuit  Hardware Description Language- VHDL) kullanılacaktır. Bölütleme sonucunun değerlendirilmesi için Uniformity Measure (UM) kullanılmıştır. UM değerlendirme sonucunun başarılı olduğu görülmüştür. Anahtar Kelimeler: Alan Programlanabilir Kapı Dizileri, FPGA, çok yüksek hızlı tümleşik devre tanımlama dili, vhdl, segmentasyon, destek vektör makinesi

scholarly journals Performance evaluation and analysis of 64-quadrature amplitude modulator using Xilinx Spartan FPGA

2018 ◽  
Vol 7 (2.8) ◽  
pp. 570
Author(s):  
Joseph Anthony Prathap ◽  
T S.Anandhi ◽  
K Ramash Kumar ◽  
B Srikanth
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Set Top Box ◽  
Field Programmable ◽  
Amplitude Modulator ◽  
Hardware Description ◽  
Cellular Technology ◽  
Very High

This paper proposes the design of 64-Quadrature Amplitude Modulation using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding and XILINX SPARTAN Field Programmable Gate Array (FPGA) real-time implementation for validation. QAM is used in modern digital communication applications like set-top box, satellite TV, wireless and cellular technology etc. In this paper, 64-QAM is implemented and compared with three different XILINX SPARTAN FPGA devices say 3A DSP, 3E and 6E. The power, current and thermal parameters are performed and compared. The power consumed for the design of 64 QAM using the Xilinx SPARTAN 6E FPGA device is 0.014W and 15.9 C/W of Effective TJA for the XILINX SPARTAN 3A DSP FPGA. The device utilization of the 64-QAM design using the XILINX SPARTAN 3A DSP is low.

scholarly journals Design and Implementation of MIPS Processor for LU Decomposition based on FPGA

2020 ◽  
Vol 4 (3) ◽  
Author(s):  
Rusul Saad Khalil ◽  
Safaa S. Omran
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Linear Equations ◽  
Lu Decomposition ◽  
Gate Arrays ◽  
The Matrix ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Hardware Description ◽  
Lower Triangle

The solution for a set of liner equations require to find the matrix inverse of a square matrix with same number of the linear equations, this operation require many mathematical calculations. To solve this problem, LU decomposition for the matrix is used, which computes two matrices, a lower triangle matrix and an upper triangle matrix. In this, paper a design for 32-bits MIPS (microprocessor without interlocked pipelined stages) processor with the required instructions that used to calculate the LU matrices. The design implemented using VHDL (Very high speed integrated circuit hardware description language) then integrated with FPGA (Field Programmable Gate Arrays) Xilinx Spartan 6. The results for the different parts of the processor are resented in the form of test bench waveform and the architecture of the system is demonstrated and the results was matched with theoretical results.

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