Asynchronous quasi delay insensitive majority voters corresponding to quintuple modular redundancy for mission/safety-critical applications

Electronic circuits and systems employed in mission- and safety-critical applications such as space, aerospace, nuclear plants etc. tend to suffer from multiple faults due to radiation and other harsh external phenomena. To overcome single or multiple faults from affecting electronic circuits and systems, progressive module redundancy (PMR) has been suggested as a potential solution that recommends the use of different levels of redundancy for the vulnerable portions of a circuit or system depending upon their criticality. According to PMR, triple modular redundancy (TMR) can be used where a single fault is likely to occur and should be masked, and quintuple modular redundancy (QMR) can be used where double faults are likely to occur and should be masked. In this article, we present asynchronous QDI majority voter designs for QMR and state which are preferable from cycle time (i.e., speed), area, power, and energy perspectives. Towards this, we implemented example QMR circuits in a robust QDI asynchronous design style by employing a delay insensitive dual rail code for data encoding and adopting four-phase handshake protocols for data communication. Based on physical implementations using a 32/28nm CMOS process, we find that our proposed QMR majority voter achieves improved optimization in speed and energy.

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Quasi Delay Insensitive Majority Voters for Triple Modular Redundancy Applications

Applied Sciences ◽

10.3390/app9245400 ◽

2019 ◽

Vol 9 (24) ◽

pp. 5400 ◽

Cited By ~ 2

Author(s):

Padmanabhan Balasubramanian ◽

Douglas L. Maskell ◽

Nikos E. Mastorakis

Keyword(s):

Oxide Semiconductor ◽

Normal Operation ◽

Synthesis Methods ◽

Correct Operation ◽

Triple Modular Redundancy ◽

Majority Voter ◽

Function Modules ◽

Function Module ◽

Modular Redundancy ◽

Design Style

Mission- and safety-critical applications tend to incorporate triple modular redundancy (TMR) in their hardware implementation to reliably withstand the fault or failure of any one of the function modules during normal operation, and the function module may be a circuit or a system. In a TMR implementation, two identical copies of a function module are used in addition to the original function module, and the correct operation of at least two function modules is required. In TMR, the corresponding primary outputs of the three function modules are combined using majority voters, which determine the actual primary outputs based on the Boolean majority. Hence, the majority voter is an important component that is useful for conveying the correct operation of a TMR implementation. In the existing literature, many designs of three-input majority voters for TMR have been discussed. However, most of these correspond to the synchronous design style and just one corresponds to the bundled-data asynchronous design style, which is not delay insensitive and hence non-robust. To our knowledge, a robust delay insensitive design of the three-input majority voter has not been considered. In this context, this article presents the designs of robust quasi delay insensitive (QDI) three-input majority voters based on QDI logic synthesis methods, and analyzes which majority voters are preferable in terms of speed, power, and area. We implement example QDI TMR circuits using a QDI full adder as the function module and QDI majority voters using 32/28 nm complementary metal oxide semiconductor (CMOS) technology. The QDI TMR implementations use the delay insensitive dual rail code for data encoding, and four-phase return-to-zero and four-phase return-to-one handshake protocols for data communication.

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Area, Power and Speed Optimized Early Output Majority Voter for Asynchronous TMR Implementation

Electronics ◽

10.3390/electronics10121425 ◽

2021 ◽

Vol 10 (12) ◽

pp. 1425

Author(s):

Padmanabhan Balasubramanian ◽

Nikos E. Mastorakis

Keyword(s):

Cycle Time ◽

Power Dissipation ◽

Data Communication ◽

Cmos Technology ◽

Silicon Area ◽

Power Cycle ◽

Data Encoding ◽

Power Product ◽

Majority Voter ◽

Modular Redundancy

This paper presents a new, efficient asynchronous early output majority voter that can be used to effectively realize an asynchronous triple modular redundancy (TMR) implementation. For the input-output mode asynchronous realization, the dual-rail code was used for data encoding and four phase return-to-zero and return-to-one handshake schemes were separately used for data communication. The proposed majority voter requires 62.8% less area and dissipates 37% less power on average compared to the best of the existing asynchronous majority voters while considering both handshake schemes. Importantly, the reductions in area and power are achieved without sacrificing the speed. Example TMR implementations show that the proposed majority voter leads to simultaneous reductions in cycle time, silicon area, and power dissipation. As a result, the proposed majority voter enables improved optimization in figure-of-merits such as area–cycle time product, power–cycle time product, and area–cycle time–power product for TMR implementations utilizing it compared to TMR implementations incorporating other majority voters. The circuits were implemented using a 32/28-nm CMOS technology.

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Generalized Majority Voter Design Method for N-Modular Redundant Systems Used in Mission- and Safety-Critical Applications

Computers ◽

10.3390/computers8010010 ◽

2019 ◽

Vol 8 (1) ◽

pp. 10 ◽

Cited By ~ 5

Author(s):

Jaytrilok Choudhary ◽

Padmanabhan Balasubramanian ◽

Danny Varghese ◽

Dhirendra Singh ◽

Douglas Maskell

Keyword(s):

Design Method ◽

Majority Voting ◽

Normal Operation ◽

Majority Logic ◽

Simultaneous Production ◽

Safety Critical ◽

Majority Voter ◽

Logic Equation ◽

Modular Redundancy ◽

Common Logic

Mission- and safety-critical circuits and systems employ redundancy in their designs to overcome any faults or failures of constituent circuits and systems during the normal operation. In this aspect, the N-modular redundancy (NMR) is widely used. An NMR system is comprised of N identical systems, the corresponding outputs of which are majority voted to generate the system outputs. To perform majority voting, a majority voter is required, and the sizes of majority voters tend to vary depending on an NMR system. Majority voters corresponding to NMR systems are physically realized by enumerating the majority input clauses corresponding to an NMR system and then synthesizing the majority logic equation. The issue is that the number of majority input clauses corresponding to an NMR system is governed by a mathematical combination, the complexity of which increases substantially with increases in the level of redundancy. In this context, the design of a majority voter of any size corresponding to an NMR specification based on a new, generalized design approach is described. The proposed approach is inherently hierarchical and progressive since any NMR majority voter can be constructed from an (N − 2)MR majority voter along with additional logic corresponding to the two extra inputs. Further, the proposed approach paves the way for simultaneous production of the NMR system outputs corresponding to different degrees of redundancy, which is not intrinsic to the existing methods. This feature is additionally useful for any sharing of common logic with diverse degrees of redundancy in appropriate portions of an NMR implementation.

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Majority and Minority Voted Redundancy Scheme for Safety-Critical Applications with Error/No-Error Signaling Logic

Electronics ◽

10.3390/electronics7110272 ◽

2018 ◽

Vol 7 (11) ◽

pp. 272 ◽

Cited By ~ 2

Author(s):

Padmanabhan Balasubramanian ◽

Douglas Maskell ◽

Nikos Mastorakis

Keyword(s):

Critical Path ◽

Cmos Technology ◽

Path Delay ◽

Silicon Area ◽

Multiple Faults ◽

Design Metrics ◽

Safety Critical ◽

Critical Path Delay ◽

Function Blocks ◽

Modular Redundancy

In the era of nanoelectronics, multiple faults or failures of function blocks are likely to occur. To withstand these, higher levels of redundancy are suggested to be employed in at least the sensitive portions of a circuit or system. In this context, the N-modular redundancy (NMR) scheme may be used to guard against the multiple faults or failures of function blocks. However, the NMR scheme would exacerbate the weight, cost, and design metrics to implement higher-order redundancy. Hence, as an alternative to the NMR, the majority and minority voted redundancy (MMR) scheme was proposed recently. However, the proposal was restricted to the basic implementation with no provision for indicating the correct or the incorrect operation of the MMR. Hence in this work, we present the MMR scheme with the error/no-error signaling logic (ESL). Example NMR circuits without and with the ESL (NMRESL), and example MMR circuits without and with the proposed ESL (MMRESL) were implemented to achieve similar degrees of fault tolerance using a 32/28-nm CMOS technology. The results show that, on average, the proposed MMRESL circuits have 18.9% less critical path delay, dissipate 64.8% less power, and require 49.5% less silicon area compared to their counterpart NMRESL circuits.

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Study of single event upsets (SEUS) a survey and analysis

10.32920/ryerson.14652159 ◽

2021 ◽

Author(s):

Sheldon Mark Foulds

Keyword(s):

Error Control ◽

Hamming Code ◽

Single Event ◽

Electronic Circuits ◽

Error Control Coding ◽

Computing Systems ◽

Single Event Upsets ◽

Triple Modular Redundancy ◽

Radiation Induced ◽

Modular Redundancy

Over the last few years evolution in electronics technology has led to the shrinkage of electronic circuits. While this has led to the emergence of more powerful computing systems it has also caused a dramatic increase in the occurrence of soft errors and a steady climb in failure in time (FIT) rates. This problem is most prevalent in FPGA based systems which are highly susceptible to radiation induced errors. Depending upon the severity of the problem a number of methods exist to counter these effects including Triple Modular Redundancy (TMR), Error Control Coding (ECC), scrubbing systems etc. The following project presents a simulation of an FPGA based system that employs one of the popular error control code techniques called the Hamming Code. A resulting analysis shows that Hamming Code is able to mitigate the effects of single event upsets (SEUs) but suffers due to a number of limitations.

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A Novel Scheme for Fault Tolerant Computing

Journal of the Institute of Electronics and Computer ◽

10.33969/jiec.2021.31002 ◽

2021 ◽

Vol 3 (1) ◽

pp. 17-23

Author(s):

Pramode Ranjan Bhattacharjee ◽

Keyword(s):

Fault Tolerant ◽

Present Scheme ◽

Triple Modular Redundancy ◽

Test Input ◽

Digital Network ◽

Additional Control ◽

Majority Voter ◽

Modular Redundancy ◽

Primary Output

A novel scheme for ensuring reliability in the operation of a combinational digital network has been offered in this paper. This has been achieved by making use of three copies of the same digital network along with two additional sub-networks, one of which consists of three additional control inputs, which can also be used as additional observable outputs. If both the said two sub-networks are fault free, then the primary output of the network in the present scheme will always give fault-free responses even if a fault (single or multiple) occurs in one of the three copies of the digital network under consideration. Unlike the Triple Modular Redundancy (TMR) scheme, the present scheme does not require any majority voter circuit. Furthermore, unlike the TMR scheme, the additional sub-networks in the present scheme can be tested off-line by predefined test input patterns.

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Integrated in-Flight Fault Detection and Accommodation: A Model-Based Study

Journal of Engineering for Gas Turbines and Power ◽

10.1115/1.2720517 ◽

2007 ◽

Vol 129 (4) ◽

pp. 962-969 ◽

Cited By ~ 5

Author(s):

Randal T. Rausch ◽

Kai F. Goebel ◽

Neil H. Eklund ◽

Brent J. Brunell

Keyword(s):

High Fidelity Simulation ◽

Multiple Faults ◽

Safety Critical ◽

Fault Accommodation ◽

Model Based ◽

High Pressure Compressor ◽

Flight Envelope ◽

Binary Classifiers ◽

Millisecond Range ◽

Integrated Detection

In-flight fault accommodation of safety-critical faults requires rapid detection and remediation. Indeed, for a class of safety-critical faults, detection within a millisecond range is imperative to allow accommodation in time to avert undesired engine behavior. We address these issues with an integrated detection and accommodation scheme. This scheme comprises model-based detection, a bank of binary classifiers, and an accommodation module. The latter biases control signals with pre-defined adjustments to regain operability while staying within established safety limits. The adjustments were developed using evolutionary algorithms to identify optimal biases off-line for multiple faults and points within the flight envelope. These biases are interpolated online for the current flight conditions. High-fidelity simulation results are presented showing accommodation applied to a high-pressure compressor fault on a commercial, high-bypass, twin-spool, turbofan engine throughout the flight envelope.

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Integrated In-Flight Fault Detection and Accommodation: A Model-Based Study

Volume 1: Turbo Expo 2005 ◽

10.1115/gt2005-68300 ◽

2005 ◽

Cited By ~ 3

Author(s):

Randal T. Rausch ◽

Kai F. Goebel ◽

Neil H. Eklund ◽

Brent J. Brunell

Keyword(s):

High Fidelity Simulation ◽

Turbofan Engine ◽

Multiple Faults ◽

Safety Critical ◽

Fault Accommodation ◽

Model Based ◽

Flight Envelope ◽

Binary Classifiers ◽

Millisecond Range ◽

Integrated Detection

In-flight fault accommodation of safety-critical faults requires rapid detection and remediation. Indeed, for a class of safety critical faults, detection within a millisecond range is imperative to allow accommodation in time to avert undesired engine behavior. We address these issues with an integrated detection and accommodation scheme. This scheme comprises model-based detection, a bank of binary classifiers, and an accommodation module. The latter biases control signals with pre-defined adjustments to regain operability while staying within established safety limits. The adjustments were developed using evolutionary algorithms to identify optimal biases off-line for multiple faults and points within the flight envelope. These biases are interpolated online for the current flight conditions. High-fidelity simulation results are presented showing accommodation applied to a high-pressure turbine fault on a commercial, high-bypass, twin-spool, turbofan engine throughout the flight envelope.

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