scholarly journals A New Phase-Locked Loop with Active Inductor Ring Oscillator

2021 ◽  
Author(s):  
Mohamad El-Hage
Keyword(s):  
Phase Noise ◽  
High Speed ◽  
Low Voltage ◽  
Building Blocks ◽  
Phase Locked Loop ◽  
Timing Jitter ◽  
Ring Oscillator ◽  
Control Voltage ◽  
Active Inductor ◽  
Switching Noise

Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO) are important building blocks in PLLs. More importantly, the VCO is the major contributor of phase noise in a PLL. The noisy environment, mainly due to the switching noise generated by the digital portion of these systems. imposes stringent constraints on the design of VCOs, especially phase noise or timing jitter. The switching noise originated in the digital portion of the systems are coupled to the supply and ground rails of the VCO of PLLs. Another important block of a PLL is the charge-pump, a block that is responsible for generating the control voltage to be applied to the VCO. The stability or fluctuation of the control voltage, can severely affect the phase noise performance of the VCO. The research in this thesis, centered on (i) the design considerations of CMOS charge-pumps, (ii) the timing jitter of the delay-cells of low-voltage CMOS ring-VCOs and (iii) the design of a high-speed ring oscillator. A PLL was designed using a new active inductor 6.3-GHz ring oscillator, with a tuning range of +/- 15% was designed in 0.18um CMOS technology. The ring oscillator employed active inductor loads that resulted in an improvement of about 42% in oscillation frequency when compared to the conventional resistor loaded ring oscillator.

scholarly journals A New Phase-Locked Loop with Active Inductor Ring Oscillator

2021 ◽  
Author(s):  
Mohamad El-Hage
Keyword(s):  
Phase Noise ◽  
High Speed ◽  
Low Voltage ◽  
Building Blocks ◽  
Phase Locked Loop ◽  
Timing Jitter ◽  
Ring Oscillator ◽  
Control Voltage ◽  
Active Inductor ◽  
Switching Noise

Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO) are important building blocks in PLLs. More importantly, the VCO is the major contributor of phase noise in a PLL. The noisy environment, mainly due to the switching noise generated by the digital portion of these systems. imposes stringent constraints on the design of VCOs, especially phase noise or timing jitter. The switching noise originated in the digital portion of the systems are coupled to the supply and ground rails of the VCO of PLLs. Another important block of a PLL is the charge-pump, a block that is responsible for generating the control voltage to be applied to the VCO. The stability or fluctuation of the control voltage, can severely affect the phase noise performance of the VCO. The research in this thesis, centered on (i) the design considerations of CMOS charge-pumps, (ii) the timing jitter of the delay-cells of low-voltage CMOS ring-VCOs and (iii) the design of a high-speed ring oscillator. A PLL was designed using a new active inductor 6.3-GHz ring oscillator, with a tuning range of +/- 15% was designed in 0.18um CMOS technology. The ring oscillator employed active inductor loads that resulted in an improvement of about 42% in oscillation frequency when compared to the conventional resistor loaded ring oscillator.

scholarly journals Design of High frequency Voltage Controlled Oscillators for Phase Locked Loop

2018 ◽  
Vol 7 (3.12) ◽  
pp. 871
Author(s):  
Thejusraj. H ◽  
Prithivi Raj ◽  
J Selvakumar ◽  
S Praveen Kumar
Keyword(s):  
Power Consumption ◽  
High Frequency ◽  
High Speed ◽  
Phase Locked Loop ◽  
Clock Recovery ◽  
Ring Oscillator ◽  
Voltage Controlled Oscillator ◽  
Voltage Controlled Oscillators ◽  
Clock Generation ◽  
Consumption Values

This paper presents the analysis of various oscillators that generate high frequency of oscillation for high speed communication, clock generation and clock recovery. The Ring oscillator and the Current Starved Voltage Controlled Oscillator(CSVCO) (for 5-stagewithout resistor and with resistor) have been implemented using the Cadence Virtuoso tool in 90 nm technology. The generated frequency of oscillation and the power consumption values of the voltage controlled oscillators have been calculated after inclusion in the PLL, and were also compared to identify the most suitable voltage controlled oscillator for a given application.

scholarly journals Low-Voltage High-Speed Ring Oscillator With a-InGaZnO TFTs

2020 ◽  
Vol 8 ◽  
pp. 584-588
Author(s):  
Bhawna Tiwari ◽  
Pydi Ganga Bahubalindruni ◽  
Angelo Santos ◽  
Ana Santa ◽  
Catia Figueiredo ◽  
...  
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Ring Oscillator

A NOVEL DESIGN METHODOLOGY FOR REDUCING SIMULTANEOUS SWITCHING NOISE EVALUATED BY A DIFFERENTIAL-IBIS STRUCTURE

2010 ◽  
Vol 19 (06) ◽  
pp. 1275-1297
Author(s):  
WEN-TZENG HUANG ◽  
SUN-YEN TAN ◽  
YUAN-JEN CHANG
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Low Voltage ◽  
Switching Noise ◽  
Decoupling Capacitors ◽  
Input Noise ◽  
Low Voltage Operation ◽  
Simultaneous Switching Noise ◽  
Simultaneous Switching ◽  
Ibis Model

Modern electronic products increasingly require high speed, high density, and low-voltage operation. In such designs, the power-delivery system could be affected by input noise to the point that it becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity. Although decoupling capacitors cannot effectively alleviate the problem of SSN, they have been generally used in the HP Simulation Program with Integrated Circuit Emphasis model for reducing SSN. The differential I/O buffer information specification (D-IBIS) model uses equivalent circuits to describe the behavior of an integrated circuit. In this study, we propose a novel method for effectively reducing SSN evaluated by an enhanced D-IBIS model with decoupling capacitors and a high-frequency low-impendence circuit. We show that this new method reduces noise by about 40–64% compared to traditional design methodologies.

scholarly journals A low-voltage CMOS current-mode differential front-end for optical communications

2021 ◽  
Author(s):  
Bendong Sun
Keyword(s):  
Optical Communications ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Building Blocks ◽  
Switching Noise ◽  
Current Feedback ◽  
Fully Differential ◽  
Digital Circuitry

This thesis deals with the design of a low-voltage fully-differential CMOS current-mode preamplifier for optical communications. An in-depth comparative analysis of the building blocks of low-voltage CMOS current-mode circuits is carried out. Two new bandwidth enhancement techniques, namely inductor series-peaking and current feedback, are introduced and implemented in the design. The feedback also reduces the value of the series-peaking inductor. The minimum supply voltage of the amplifier is only one threshold voltage plus one pinch-off voltage. The preamplifier has a balanced differential topology such that the effect of bias dependent mismatches is minimized and the amplifier is insensitive to the switching noise caused by the digital circuitry. Negative differential current feedbacks are implemented to boost the bandwidth and increase the dynamic range.

Efficient techniques of fractional-N PLL for pervasive wireless applications

2022 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Azeem Mohammed Abdul ◽  
Usha Rani Nelakuditi
Keyword(s):  
Phase Noise ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Oxide Semiconductor ◽  
Wireless Devices ◽  
Phase Frequency Detector ◽  
Content Type ◽  
Wireless Applications ◽  
Frequency Detector

Purpose The purpose of this paper to ensure the rapid developments in the radio frequency wireless technology, the synthesis of frequencies for pervasive wireless applications is crucial by implementing the design of low voltage and low power Fractional-N phase locked loop (PLL) for controlling medical devices to monitor remotely patients. Design/methodology/approach The developments urge a technique reliable to phase noise in designing fractional-N PLL with a new eight transistor phase frequency detector and a good linearized charge pump (CP) for speed of operation with minimum mismatches. Findings In applications for portable wireless devices, by proposing a new phase-frequency detector with the removal of dead, blind zones and a modified CP to minimize the mismatch of currents. Originality/value The results are simulated in 45 nm complementary metal oxide semiconductor generic process design kit (GPDK) technology in cadence virtuoso. The phase noise of the proposed Fractiona-N phase locked loop has–93.18, –101.4 and –117 dBc/Hz at 10 kHz, 100 kHz and 1 MHz frequency offsets, respectively, and consumes 3.3 mW from a 0.45 V supply.

scholarly journals A Low Jitter – Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer Cmos Technology

2019 ◽  
Vol 8 (4) ◽  
pp. 3994-3999
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
High Speed ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Critical Parameters ◽  
Nanometer Cmos ◽  
Dc Power ◽  
Low Jitter ◽  
Low Phase Noise

For high speed communication applications; jitter, phase noise and power consumption are most critical parameters required to be considered for PLL designs. A sub harmonically injection locking concept can be used in PLL to reduce jitter and phase noise. Such design is very effective for high frequency applications. This article presents similar design for 7.5-GHz Phase locked loop in 180 nm CMOS technology. The measured phase noise of the proposed PLL with self aligned injection at 1 MHz offset is 121.14 dBc/Hz and rms jitter is 110 fs. The total dc power consumption is 13.99 mW. To support the claim process variation with design corner analysis using random variations are carried out.

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