scholarly journals Method for reducing the amplitudes of higher harmonics in the output voltage of the frequency converter

2021 ◽  
Vol 29 (1) ◽  
pp. 120-132
Author(s):  
Alexsandr V. Starikov ◽  
Sergey L. Lisin ◽  
Olga S. Belyaeva ◽  
Viktor A. Kirdyashev
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Dead Time ◽  
Frequency Converter ◽  
Higher Harmonics ◽  
Sinusoidal Modulation ◽  
Power Transistors ◽  
Switching Power ◽  
Sinusoidal Pulse Width Modulation

Modern low-voltage frequency converters, built on the principle of stand-alone inverters with pulse-width modulation, have large amplitudes of higher harmonics in the output voltage. This adversely affects the operation of an asynchronous or synchronous motor connected to such a converter, since it causes a decrease in the efficiency of the AC machine. The analysis of the reasons for the poor harmonic composition of the output voltage of traditional inverters with sinusoidal pulse-width modulation is carried out and it is noted that the main one is the introduction of "dead" time when switching half-bridges every modulation period. The proposed method of sinusoidal modulation does not require the introduction of "dead" time. The modes of operation of power transistors with this switching method and control signal diagrams are considered. Analytical expressions are found that make it possible to determine the effective value of the output voltage of the frequency converter and the coefficients of higher harmonics for the proposed method of switching power transistors. The main reason for the low effective value of the phase voltage at the output of the inverter at sinusoidal pulse-width modulation is determined - the ineffective use of the switching period. The proposed method of sinusoidal modulation does not require the introduction of "dead" time, increasing the effective value of the output voltage and reducing the total harmonic component by 75 times. The diagrams of signals that control power transistors and provide a decrease in the amplitudes of higher harmonics at the output of the frequency converter are given. An approximation by the harmonic Fourier series of the output voltage of the inverter, obtained in the case of using the proposed method of switching power transistors, is made. It is noted that for the technical implementation of sinusoidal modulation, which provides small amplitudes of higher harmonics, only two pulse-width modulators are needed.

Tri‐carrier sinusoidal pulse‐width modulation without dead time effects for converters

2015 ◽  
Vol 8 (10) ◽  
pp. 1941-1951 ◽  
Author(s):  
Chonghui Song ◽  
Naizhe Diao ◽  
Zhiwei Xue ◽  
Xianrui Sun ◽  
Jianning Guan
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Dead Time ◽  
Time Effects ◽  
Sinusoidal Pulse Width Modulation

scholarly journals Hardware implementation of single phase three-level cascaded h-bridge multilevel inverter using sinusoidal pulse width modulation

2019 ◽  
Vol 10 (2) ◽  
pp. 625
Author(s):  
A. Shamsul Rahimi A. Subki ◽  
Mohd Zaidi Mohd Tumari ◽  
Wan Norhisyam Abd Rashid ◽  
Aiman Zakwan Jidin ◽  
Ahmad Nizammuddin Muhammad Mustafa
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Single Phase ◽  
Hardware Implementation ◽  
Pulse Width Modulation ◽  
Sine Wave ◽  
Multilevel Inverter ◽  
Square Wave ◽  
Output Waveform ◽  
Sinusoidal Pulse Width Modulation

<span lang="EN-US">In this paper a hardware implementation of single-phase cascaded H-bridge three level multilevel inverter (MLI) using sinusoidal pulse width modulation (SPWM) is presented. There are a few interesting features of using this configuration, where less component count, less switching losses, and improved output voltage/current waveform. The output of power inverter consists of three form, that is, square wave, modified square wave and pure sine wave. The pure sine wave and modified square wave are more expensive than square wave. The focus paper is to generate a PWM signal which control the switching of MOSFET power semiconductor. The sine wave can be created by using the concept of Schmitt-Trigger oscillator and low-pass filter topology followed by half of the waveform will be eliminated by using the circuit of precision half-wave rectifier. Waveform was inverted with 180º by circuit of inverting op-amp amplifier in order to compare saw-tooth waveform. Two of PWM signal were produced by circuit of PWM and used digital inverter to invert the two PWM signal before this PWM signal will be passed to 2 MOSFET driver and a 3-level output waveform with 45 Hz was produced. As a conclusion, a 3-level output waveform is produced with output voltage and current recorded at 22.5 Vrms and 4.5 Arms. The value of measured resistance is 0.015 Ω that cause voltage drop around 0.043 V. Based on the result obtained, the power for designed inverter is around 100W and efficiency recorded at 75%.</span>

scholarly journals Design and Simulation of Novel 11-level Inverter Scheme with Reduced Switches

2018 ◽  
Vol 8 (5) ◽  
pp. 3536
Author(s):  
R. Palanisamy ◽  
Gaurav Singh ◽  
Priyanka Das ◽  
D. Selvabharathi ◽  
Sourav Sinha ◽  
...  
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Output Current ◽  
Controlled Switching ◽  
Switching Losses ◽  
Voltage Stress ◽  
Sinusoidal Pulse Width Modulation ◽  
Switching Devices

This work recommends the performance of coupled inductor based novel 11-level inverter with reduced number of switches. The inverter which engender the sinusoidal output voltage by the use of split inductor with minimised total harmonic distortion (THD). The voltage stress on each controlled switching devices, capacitor balancing and switching losses can be reduced. The proposed system which gives better controlled output current and improved output voltage with moderate THD value. The switching devices of the system are controlled by using multicarrier sinusoidal pulse width modulation algorithm by comparing the carrier signals with sinusoidal signal. The simulation and experimental results of the proposed 11-level inverter system outputs are established using matlab/Simulink and dsPIC microcontroller respectively.<br /><br />

scholarly journals Multilevel neutral point clamped/H-bridge inverters with sinusoidal pulse width modulation

2021 ◽  
Author(s):  
Arifur Rahman Shohel
Keyword(s):  
Computer Simulation ◽  
Theoretical Analysis ◽  
High Power ◽  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Neutral Point ◽  
Medium Voltage ◽  
Modulation Technique ◽  
Sinusoidal Pulse Width Modulation

This project focuses on the topology of multilevel neutral point clamped (NPC)/H-bridge inverters and their modified modulation technique for high-power (megawatts) medium voltage (typically 6000 v) applications. A sinusodial pulse width in-phase disposition modulation is proposed for five-level NPC/H-bridge inverters. The inverter achieves good harmonic performance and low dv/dt in its output voltage waveforms in comparison to the conventional three-level NPC inverter. A seven-level NPC/H-bridge topology and its sinusodial pulse width in-phase disposition modulation are also proposed and investigated, which has better performance than the five-level inverters. Theoretical analysis and computer simulation are carried out for the proposed inverter topologies and algorithms. The output voltage waveforms and harmonic performance are verified by experiments on a five-level NPC/H-bridge inverters.

scholarly journals New Dead-Time Compensation Method of Power Inverter using Carrier Based Sinusoidal Pulse-Width Modulation

2018 ◽  
Vol 8 (6) ◽  
pp. 4880
Author(s):  
Suroso Suroso ◽  
Daru Tri Nugroho ◽  
Toshihiko Noguchi
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Dead Time ◽  
Compensation Method ◽  
Voltage Source ◽  
Output Current ◽  
Dead Time Correction ◽  
Source Power ◽  
Dead Time Compensation ◽  
Sinusoidal Pulse Width Modulation

<p>A new dead-time compensation method of power inverter circuits is suggested and presented in this paper. The proposed method utilizes carrier based sinusoidal pulse width modulation technique to produce driving signals of the inverter power switches with dead-time correction capability. The proposed method able to eliminate dead-time effects such as reducing the waveform distortion of the inverter output current, and increasing the fundamental component amplitude of output current. An analysis of the proposed method is presented. Some computer simulations were carried out to investigate the principle operation, and to test performance of the new method. The developed method was validated through experimental test of H-bridge voltage source inverter circuits. The data obtained from the computer simulation and prototype experiments have confirmed that that the proposed method worked well compensating the dead-time in the voltage source power inverter circuits.</p>

Modulation Waveform Cycle Normalization Based Unipolar SPWM Controller

2013 ◽  
Vol 791-793 ◽  
pp. 681-685
Author(s):  
Chao Jiang ◽  
Yue Li Hu ◽  
Ke Ke Zhang ◽  
Yang Cao
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Design Method ◽  
Practical Significance ◽  
The Novel ◽  
Sinusoidal Modulation ◽  
Sinusoidal Pulse Width Modulation ◽  
Novel Design

The thesis mainly proposed a novel design method for Sinusoidal Pulse Width Modulation (SPWM) controller based on modulation waveform cycle normalization. T is the period of sinusoidal modulation waveform, and T/n is the cycle of triangular carrier. Shift registers and adders of SPWM controller were designed to translate the 2n numerical value for SPWM waveform on-off switching points, which were calculated offline, to control the level of the outpout SPWM waveform,which is the key point of modulation waveform cycle normalization. In the thesis RTL function simulation verification by ModelSim and testing for FPGA have been achieved successfully. The results show that the novel SPWM controller is reliable, which has practical significance.

scholarly journals Three-Phase Symmetric Cascading Z-Source Seven Levels Multilevel Inverter Excited by Multi Carrier Sinusoidal Pulse Width Modulation Scheme

2019 ◽  
Vol 8 (10) ◽  
pp. 4269-4274
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Multilevel Inverter ◽  
Modulation Scheme ◽  
Performance Parameters ◽  
Output Waveform ◽  
Three Phase ◽  
Sinusoidal Pulse Width Modulation ◽  
Z Sources

The Multilevel Z sources Inverter have been documented as attractive topologies used for elevated voltage adaptation. As the digit of levels improved, the synthesized set of steps output waveform have many ladder, imminent the preferred sine waveform but the major weakness of MLI be its amplitude of ac output voltage is imperfect to DC input sources voltage summing up. To conquer this drawback seven level cascading symmetric multilevel inverter based Z source inverter have been projected. This work focuses on different multi-carrier sinusoidal PWM scheme for the seven level three phase Z source symmetric cascading inverter. Performance parameters of seven level three phase Z source symmetric cascading inverter has been analyzed. A simulation circuit model of seven level three phase Z source symmetric cascading inverter urbanized using MATLAB/SIMULINK and its presentation have been urbanized.

scholarly journals Analysis of Symmetric and Asymmetric Multilevel Inverter Topologies Using Reduced Number of Switching Devices Circuit Structure

2018 ◽  
Vol 7 (4.30) ◽  
pp. 234
Author(s):  
M. H. Yatim ◽  
A. Ponniran ◽  
A. A. Bakar ◽  
A. N. Kasiran ◽  
K. R. Noor ◽  
...  
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Total Harmonic Distortion ◽  
Voltage Level ◽  
Switching Strategy ◽  
Circuit Structure ◽  
Sinusoidal Pulse Width Modulation ◽  
Switching Devices

This paper presents symmetric and asymmetric multilevel inverter principles using reduced number of switching devices circuit structure. Principally, asymmetric multilevel inverter topology able to produce higher output voltage level without modification of the structure in order to reduce total harmonic distortion at the output voltage. In contrast, the number of switching devices need to be increased with symmetric principle when higher output voltage level is considered. In this study, 5-level reduced number of switching devices circuit structure is selected as a circuit configuration for symmetric (5-level structure) and asymmetric (7-level and 9-level structures) multilevel inverters. For switching strategy, modified pulse width modulation and sinusoidal pulse width modulation are selected to produce output voltage levels of the inverter. Modified pulse width modulation used low switching frequency in producing signal and needs higher output voltage levels to achieve low total harmonic distortion. In contrast, sinusoidal pulse width modulation used high switching frequency in order to minimize total harmonic distortion. Theoretically, total harmonic distortion is reduced when number of output voltage level is increased for both cases. The findings show that, the 9-level asymmetric topology has lower total harmonic distortion compared to the 5-level symmetric topology and 7-level asymmetric topology, whereby these inverters using the same circuit configuration. The results show that, the total harmonic distortions of 9-level asymmetric topology, 7-level asymmetric topology and 5-level symmetric topology are 14.54%, 18.08% and 26.92%, respectively with sinusoidal pulse width modulation switching strategy. Meanwhile, with modified pulse width modulation switching strategy, the total harmonic distortions of 9-level asymmetric topology, 7-level asymmetric topology and 5-level symmetric topology are 18.7%, 21.68% and 28.99%, respectively. Therefore, 9-level asymmetric with sinusoidal pulse width modulation switching strategy show the lowest total harmonic distortion with optimum number of switching devices.

scholarly journals Control Techniques for the Cascaded and Cross-switched Multilevel Inverter - A Comparison

2021 ◽  
Vol 309 ◽  
pp. 01120
Author(s):  
Sameera Shaik ◽  
Suresh Kumar Tummala ◽  
D Srinivasa Rao
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Multilevel Inverter ◽  
Third Harmonic ◽  
Multilevel Inverters ◽  
Control Techniques ◽  
Harmonic Content ◽  
Sinusoidal Pulse Width Modulation ◽  
Injection Pulse

Nowadays, the multilevel inverter has gained huge attention and has become more popularized in high voltage and high-power applications with low harmonics. As the number of output voltage increases, the harmonic content of the output voltage waveform decreases. In this paper, a comparison of cascaded H-bridge and cross-switched multilevel inverters for 7, 9, 15, 21 levels will be carried out. The different control techniques that will be used for carrying out comparisons are space vector pulse width modulation (SPVPWM), sinusoidal pulse width modulation (SPWM), and third harmonic injection pulse width modulation (THI-PWM) respectively. Here, the seven-level inverter is discussed mainly and can be extended to any number of levels.

Analysis and simulation of a single-phase seven-level inverter controlled by modified sinusoidal PWM technique

2021 ◽  
pp. 2150024
Author(s):  
V. srinath ◽  
Man Mohan Agarwal ◽  
D. K. Chaturvedi
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Single Phase ◽  
Pulse Width Modulation ◽  
Optimization Technique ◽  
Reference Signal ◽  
Harmonic Distortion ◽  
Modulation Index ◽  
Reference Signals ◽  
Sinusoidal Pulse Width Modulation

In this paper, a modified Sinusoidal Pulse width Modulation (MSPWM) technique and a modified single-phase H-bridge seven-level inverter is proposed. The switching pulses for the proposed seven-level inverter are generated using a single triangular carrier waveform, a fully rectified sinusoidal signal, and three stepped reference signals (Uref1, Uref2 and Uref3). Using optimization technique, the magnitude of the stepped reference signal is determined so that the total harmonic distortion (THD) of the output voltage waveform is minimum and the fundamental component, RMS value of the voltage is improved for a given modulation index Ma as compared to the Sinusoidal Pulse width Modulation (SPWM). By the implementation of the new scheme, the seven-level of the inverter output voltage level (+Vdc, +2Vdc/3, +Vdc/3, 0, −Vdc, −2Vdc/3, −Vdc) is obtained for any given modulation index. Similarly, if only two stepped reference signals are used then the inverter will act as a five-level inverter for any modulating index ma. The proposed MSPWM and seven-level inverter are simulated on MATLAB/SIMULINK for R, R-L load and on a single-phase capacitor-start and capacitor-start-run Induction Motor.

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