Direct-access mode-division multiplexing switch for scalable on-chip multi-mode networks

Nanophotonics ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Hongnan Xu ◽  
Chaoyue Liu ◽  
Daoxin Dai ◽  
Yaocheng Shi
Keyword(s):  
Dynamic Control ◽  
Error Rates ◽  
Direct Access ◽  
Mode Division Multiplexing ◽  
Access Scheme ◽  
Measurement Results ◽  
Access Mode ◽  
Photonic Interconnects ◽  
On Chip ◽  
Multi Mode

Abstract By leveraging mode-division multiplexing (MDM), capacity of on-chip photonic interconnects can be scaled up to an unprecedented level. The demand for dynamic control of mode carriers has led to the development of mode-division multiplexing switches (MDMS), yet the conventional MDMS is incapable of directly accessing an individual lower-order mode that propagates in a multi-mode bus waveguide, which hinders its scalability and flexibility. In this paper, we propose and demonstrate the first direct-access MDMS as a novel platform for scalable on-chip multi-mode networks. At first, the highly efficient mode exchangers are developed for TE0–TE2 and TE1–TE2 mode swap, which are then employed to realize the direct-access mode add-drop multiplexers with high performances. The direct-access MDMS is then achieved based on the proposed mode add-drop multiplexers, which can be used for dynamically adding and dropping any selected mode carrier in a three-channel MDM. Moreover, the novel direct-access scheme is also adopted to simultaneously harness wavelength and mode carriers, leading to a wavelength/mode-hybrid multiplexing system with an enhanced link capacity of twelve channels. To further verify the utility of the MDMS, a multi-mode hubbed-ring network is constructed, where one hub and three nodes are organized within a ring-like multi-mode bus waveguide. The reconfigurable network traffic of 6 × 10 Gbps data streams are obtained by using three eigen modes as signal carriers. The measurement results show low bit-error rates (<10−9) with low power penalties (<3.1 dB).

scholarly journals Silicon Integrated Nanophotonic Devices for On-Chip Multi-Mode Interconnects

2020 ◽  
Vol 10 (18) ◽  
pp. 6365
Author(s):  
Hongnan Xu ◽  
Daoxin Dai ◽  
Yaocheng Shi
Keyword(s):  
Large Scale ◽  
Silicon On Insulator ◽  
Nanophotonic Devices ◽  
Mode Division Multiplexing ◽  
Higher Order Modes ◽  
Index Contrast ◽  
High Index Contrast ◽  
On Chip ◽  
Multi Mode ◽  
Development Prospects

Mode-division multiplexing (MDM) technology has drawn tremendous attention for its ability to expand the link capacity within a single-wavelength carrier, paving the way for large-scale on-chip data communications. In the MDM system, the signals are carried by a series of higher-order modes in a multi-mode bus waveguide. Hence, it is essential to develop on-chip mode-handling devices. Silicon-on-insulator (SOI) has been considered as a promising platform to realize MDM since it provides an ultra-high-index contrast and mature fabrication processes. In this paper, we review the recent progresses on silicon integrated nanophotonic devices for MDM applications. We firstly discuss the working principles and device configurations of mode (de)multiplexers. In the second section, we summarize the multi-mode routing devices, including multi-mode bends, multi-mode crossings and multi-mode splitters. The inverse-designed multi-mode devices are then discussed in the third section. We also provide a discussion about the emerging reconfigurable MDM devices in the fourth section. Finally, we offer our outlook of the development prospects for on-chip multi-mode photonics.

On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links

2012 ◽  
Vol 3 (4) ◽  
pp. 42-56 ◽  
Author(s):  
Sebastian Höppner ◽  
Dennis Walter ◽  
Georg Ellguth ◽  
René Schüffny
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Error Rates ◽  
Oxide Semiconductor ◽  
Multiprocessor System ◽  
Semiconductor Technology ◽  
Clock Jitter ◽  
Measurement Results ◽  
Delay Variations ◽  
On Chip

This paper presents techniques for measurement and compensation of timing variations in clock and data channels of source-synchronous high-speed serial network-on-chip (NoC) links. Timing mismatch measurements are performed by means of asynchronous sub-sampling. This allows the use of low quality sampling clocks to reduce test hardware overhead for integration into complex MPSoCs (Multiprocessor System-on-Chip) with multiple NoC links. The effect of clock jitter on the measurement results is evaluated. Delay mismatch is compensated by tunable delay cells. The proposed technique enables compensation of delay variations to realize high-speed NoC links with sufficient yield. It is demonstrated at NoC links as part of an MPSoC in 65 nm Complementary Metal Oxide Semiconductor technology, where the calibration significantly reduces bit-error-rates of a 72 GBit/s (8 GBit/s per lane) link over 4 mm on-chip interconnect.

Precise Cache Profiling for Studying Radiation Effects

2021 ◽  
Vol 20 (3) ◽  
pp. 1-25
Author(s):  
James Marshall ◽  
Robert Gifford ◽  
Gedare Bloom ◽  
Gabriel Parmer ◽  
Rahul Simha
Keyword(s):  
Radiation Effects ◽  
Fault Injection ◽  
Error Correcting Codes ◽  
Direct Access ◽  
Transient Faults ◽  
Large Area ◽  
Common Multiple ◽  
Single Event Upsets ◽  
On Chip ◽  
Future Work

Increased access to space has led to an increase in the usage of commodity processors in radiation environments. These processors are vulnerable to transient faults such as single event upsets that may cause bit-flips in processor components. Caches in particular are vulnerable due to their relatively large area, yet are often omitted from fault injection testing because many processors do not provide direct access to cache contents and they are often not fully modeled by simulators. The performance benefits of caches make disabling them undesirable, and the presence of error correcting codes is insufficient to correct for increasingly common multiple bit upsets. This work explores building a program’s cache profile by collecting cache usage information at an instruction granularity via commonly available on-chip debugging interfaces. The profile provides a tighter bound than cache utilization for cache vulnerability estimates (50% for several benchmarks). This can be applied to reduce the number of fault injections required to characterize behavior by at least two-thirds for the benchmarks we examine. The profile enables future work in hardware fault injection for caches that avoids the biases of existing techniques.

scholarly journals Silicon integrated multi-mode ring resonator

Nanophotonics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 1265-1272
Author(s):  
Mengyuan Ye ◽  
Chunlei Sun ◽  
Yu Yu ◽  
Yunhong Ding ◽  
Xinliang Zhang
Keyword(s):  
Integrated Circuit ◽  
Ring Resonator ◽  
Rapid Development ◽  
Essential Element ◽  
Single Mode ◽  
Modal Dispersion ◽  
Waveguide Width ◽  
Mode Division Multiplexing ◽  
Evanescent Coupling ◽  
Multi Mode

Abstract Ring resonator is an essential element in silicon integrated circuit, it is widely used as filter, wavelength multiplexer and switch in single-mode operation regime. As the rapid development of mode division multiplexing (MDM) technique, ring resonator that can process multi-mode signals simultaneously and uniformly is highly desired. However, the severe modal dispersion makes identical transmission for different modes very hard. In this paper, by breaking through the limitation of conventional multi-mode manipulation design with evanescent coupling or mode interference, we propose and demonstrate a multi-mode ring resonator (MMRR) inspired by the free space geometric optics. Arbitrary number of supporting modes can be achieved by simply widening the waveguide width. For proof-of-concept demonstration, an MMRR supporting four modes is fabricated with uniform transmittance. Furthermore, architecture of cascaded four MMRRs are also demonstrated experimentally.

scholarly journals Electro-Optofluidicis: Achieving Dynamic Control On-Chip

2013 ◽  
Vol 104 (2) ◽  
pp. 503a
Author(s):  
Mohammad Soltani ◽  
James Inman ◽  
Michal Lipson ◽  
Michelle D. Wang
Keyword(s):  
Dynamic Control ◽  
On Chip

scholarly journals Development of a Non-Invasive On-Chip Interconnect Health Sensing Method Based on Bit Error Rates

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3234
Author(s):  
Insun Shin ◽  
Kyoungmin Koo ◽  
Daeil Kwon
Keyword(s):  
Error Rates ◽  
In Situ Monitoring ◽  
Service Development ◽  
Gradual Transition ◽  
System Operation ◽  
Network Systems ◽  
Non Invasive ◽  
On Chip ◽  
Fault Diagnosis And Prognosis ◽  
Dc Resistance

Electronic products and systems are widely used in industrial network systems, control devices, and data acquisition devices across many industry sectors. Failures of such electronic systems might lead to unexpected downtime, loss of productivity, additional work for repairs, and delay in product and service development. Thus, developing an appropriate sensing technique is necessary, because it is the first step in system fault diagnosis and prognosis. Many sensing techniques often require external and additional sensing devices, which might disturb system operation and consequently increase operating costs. In this study, we present an on-chip health sensing method for non-destructive and non-invasive interconnect degradation detection. Bit error rate (BER), which represents data integrity during digital signal transmission, was selected to sense interconnect health without connecting external sensing devices. To verify the health sensing performance, corrosion tests were conducted with in situ monitoring of the BER and direct current (DC) resistance. The eye size, extracted from the BER measurement, showed the highest separation between the intact and failed interconnect, as well as a gradual transition, compared with abrupt changes in the DC resistance, during interconnect degradation. These experimental results demonstrate the potential of the proposed sensing method for on-chip interconnect health monitoring applications without disturbing system operation.

On-chip tunable multi-mode interference reflector

2018 ◽  
Vol 51 (49) ◽  
pp. 495101
Author(s):  
Fengxin Dong ◽  
Anjin Liu ◽  
Pijie Ma ◽  
Wanhua Zheng
Keyword(s):  
On Chip ◽  
Multi Mode ◽  
Mode Interference
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