High Density Direct Bond Interconnect (DBI) Technology for Three Dimensional Integrated Circuit Applications

MRS Proceedings ◽

10.1557/proc-0970-y01-04 ◽

2006 ◽

Vol 970 ◽

Cited By ~ 16

Author(s):

Paul Enquist

Keyword(s):

Wafer Bonding ◽

Integrated Circuit ◽

Three Dimensional ◽

High Density ◽

Temperature Cycling ◽

Direct Wafer Bonding ◽

Part Yield ◽

Bond Interface ◽

Bonding Technology ◽

Three Dimensional Integrated Circuit

ABSTRACTA novel direct wafer bonding technology capable of forming a very high density of electrical interconnections across the bond interface integral to the bond process is described. Results presented include an 8 um interconnection pitch, die-to-wafer and wafer-to-wafer bonding formats, temperature cycling reliability × 10 greater than the JEDEC requirement, connection yield ∼ 99.999, > 50% part yield on parts with ∼ 450,000 connections, and < 0.1 Ohm connection resistance at 1pA without requiring a voltage surge to induce current.

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Evaluation of Thin Dielectric-Glue Wafer-Bonding for Three Dimensional Integrated Circuit-Applications

MRS Proceedings ◽

10.1557/proc-812-f6.16 ◽

2004 ◽

Vol 812 ◽

Cited By ~ 6

Author(s):

Y. Kwon ◽

J. Yu ◽

J.J. McMahon ◽

J.-Q. Lu ◽

T.S. Cale ◽

...

Keyword(s):

Residual Stress ◽

Thermal Cycling ◽

Wafer Bonding ◽

Integrated Circuit ◽

Thermal Cycle ◽

Three Dimensional ◽

Chemical Vapor ◽

Adhesion Energy ◽

Chemical Vapor Deposited ◽

Three Dimensional Integrated Circuit

AbstractThe critical adhesion energy of benzocyclobutene (BCB)-bonded wafers is quantitatively investigated with focus on BCB thickness, material stack and thermal cycling. The critical adhesion energy depends linearly on BCB thickness, increasing from 19 J/m2 to 31 J/m2 as the BCB thickness increases from 0.4 μm to 2.6 μm, when bonding silicon wafers coated with plasma enhanced chemical vapor deposited (PECVD) silicon dioxide (SiO2). In thermal cycling performed with 350 and 400 oC peak temperatures, the significant increase in critical adhesion energy at the interface between BCB and PECVD SiO2 during the first thermal cycle is attributed to relaxation of residual stress in the PECVD SiO2 layer. On the other hand, the critical adhesion energy at the interface between BCB and PECVD silicon nitride (SiNx) decreases due to the increase of residual stress in the PECVD SiNx layer during the first thermal cycle.

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Low Temperature Cu–Cu Bonding Technology in Three-Dimensional Integration: An Extensive Review

Journal of Electronic Packaging ◽

10.1115/1.4038392 ◽

2018 ◽

Vol 140 (1) ◽

Cited By ~ 15

Author(s):

Asisa Kumar Panigrahy ◽

Kuan-Neng Chen

Keyword(s):

Low Temperature ◽

Integrated Circuit ◽

Large Scale ◽

Three Dimensional ◽

3D Ic ◽

Bonding Technology ◽

Three Dimensional Integrated Circuit ◽

Low Temperature Bonding ◽

Cu Bonding

Arguably, the integrated circuit (IC) industry has received robust scientific and technological attention due to the ultra-small and extremely fast transistors since past four decades that consents to Moore's law. The introduction of new interconnect materials as well as innovative architectures has aided for large-scale miniaturization of devices, but their contributions were limited. Thus, the focus has shifted toward the development of new integration approaches that reduce the interconnect delays which has been achieved successfully by three-dimensional integrated circuit (3D IC). At this juncture, semiconductor industries utilize Cu–Cu bonding as a key technique for 3D IC integration. This review paper focuses on the key role of low temperature Cu–Cu bonding, renaissance of the low temperature bonding, and current research trends to achieve low temperature Cu–Cu bonding for 3D IC and heterogeneous integration applications.

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Dielectric GlueWafer Bonding For 3D ICs

MRS Proceedings ◽

10.1557/proc-766-e5.8 ◽

2003 ◽

Vol 766 ◽

Cited By ~ 11

Author(s):

Y. Kwon ◽

A. Jinda ◽

J.J. McMahon ◽

J.Q. Lu ◽

R.J. Gutmann ◽

...

Keyword(s):

Integrated Circuit ◽

Bonding Strength ◽

Three Dimensional ◽

Wafer Level ◽

Four Point Bending ◽

Mechanical And Electrical Properties ◽

3D Ics ◽

Bond Interface ◽

Three Dimensional Integrated Circuit ◽

Wafer Thinning

AbstractA process to bond 200 mm wafers for wafer-level three-dimensional integrated circuit (3D-IC) applications is discussed. Four-point bending is used to quantify the bonding strength and identify the weak interface. Using benzocylcobutene (BCB) glue, the bonding strength depends on (1) glue thickness, (2) glue film preparation, and (3) materials and structures on the wafer(s). A seamless BCB-to-BCB bond interface provides the highest bonding strength compared to other interfaces in these structures (> 34 J/m2). Mechanical and electrical properties of a wafer with copper interconnect structures are preserved after wafer bonding and wafer thinning, confirming the potential of the bonding process for 3D ICs.

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Process Optimization for 3-D IC Assembly

Journal of Microelectronics and Electronic Packaging ◽

10.4071/imaps.474 ◽

2015 ◽

Vol 12 (4) ◽

pp. 219-225

Author(s):

Charles G. Woychik ◽

Sangil Lee ◽

Scott McGrath ◽

Sitaram Arkalgud

Keyword(s):

Process Optimization ◽

Integrated Circuit ◽

Flip Chip ◽

Three Dimensional ◽

High Density ◽

Test Facility ◽

Final Structure ◽

Three Dimensional Integrated Circuit ◽

Circuit Assembly

The challenge for three-dimensional integrated circuit assembly is how to manage warpage and thin wafer handling to achieve a high assembly yield and to ensure that the final structure can pass the specified reliability requirements. Our test vehicles have microbumped die with pitches ranging from 120 μm down to 60 μm. The high density of pads and the large die size make it extremely challenging to ensure that all of the microbump interconnects are attached to a thin Si interposer (ITP). In addition, the low standoff between the die and ITP makes it difficult to underfill. A likely approach is to first attach the die to the ITP and then the die/ITP subassembly to the substrate. In this scenario, the die/ITP subassembly is comparable to a monolithic Si die that can be flip chip attached to the substrate. In this article, we discuss various assembly options and the challenges posed by each. In this investigation, we will propose the best method to do two-and-half-dimensional assembly in an outsourced assembly and test facility.

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