3-D Integration Technology for High Performance Detector Arrays

2006 ◽  
Vol 970 ◽  
Author(s):  
Dorota Temple ◽  
Christopher A. Bower ◽  
Dean Malta ◽  
James E. Robinson ◽  
Phillip R. Coffman ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Focal Plane ◽  
High Performance ◽  
Three Dimensional ◽  
Focal Plane Arrays ◽  
Detector Arrays ◽  
Silicon Integrated Circuits ◽  
Military Systems ◽  
On Chip ◽  
Chip Signal

ABSTRACTThis paper describes a technology for three-dimensional (3-D) integration of multiple layers of silicon integrated circuits. The technology promises to dramatically enhance on-chip signal processing capabilities of a variety of detector devices hybridized with Si electronics. The focus of the paper is on high performance infrared focal plane arrays based on HgCdTe, which offer the ultimate in infrared sensitivity and find application in high performance military systems. Performance data from test FPA devices with integrated multilayer Si stacks are discussed in this paper.

scholarly journals High-Performance On-Chip Silicon Beamsplitter Based on Subwavelength Metamaterials for Enhanced Fabrication Tolerance

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1304
Author(s):  
Raquel Fernández de Cabo ◽  
David González-Andrade ◽  
Pavel Cheben ◽  
Aitor V. Velasco
Keyword(s):  
Integrated Circuits ◽  
Fundamental Mode ◽  
High Performance ◽  
Three Dimensional ◽  
High Sensitivity ◽  
Power Splitting ◽  
Excess Loss ◽  
Power Splitters ◽  
On Chip ◽  
Efficient Power

Efficient power splitting is a fundamental functionality in silicon photonic integrated circuits, but state-of-the-art power-division architectures are hampered by limited operational bandwidth, high sensitivity to fabrication errors or large footprints. In particular, traditional Y-junction power splitters suffer from fundamental mode losses due to limited fabrication resolution near the junction tip. In order to circumvent this limitation, we propose a new type of high-performance Y-junction power splitter that incorporates subwavelength metamaterials. Full three-dimensional simulations show a fundamental mode excess loss below 0.1 dB in an ultra-broad bandwidth of 300 nm (1400–1700 nm) when optimized for a fabrication resolution of 50 nm, and under 0.3 dB in a 350 nm extended bandwidth (1350–1700 nm) for a 100 nm resolution. Moreover, analysis of fabrication tolerances shows robust operation for the fundamental mode to etching errors up to ± 20 nm. A proof-of-concept device provides an initial validation of its operation principle, showing experimental excess losses lower than 0.2 dB in a 195 nm bandwidth for the best-case resolution scenario (i.e., 50 nm).

On-chip signal processing configurations for focal plane arrays

1999 ◽  
Author(s):  
Christopher R. Baxter ◽  
Mark A. Massie
Keyword(s):  
Signal Processing ◽  
Focal Plane ◽  
Focal Plane Arrays ◽  
On Chip ◽  
Chip Signal

Dependence of the Deformation of 128×128 InSb Focal-plane Arrays on the Silicon Readout Integrated Circuit Thickness

2015 ◽  
Vol 9 (1) ◽  
pp. 170-174 ◽  
Author(s):  
Xiaoling Zhang ◽  
Qingduan Meng ◽  
Liwen Zhang
Keyword(s):  
Thermal Shock ◽  
Indium Antimonide ◽  
Integrated Circuit ◽  
Focal Plane ◽  
Three Dimensional ◽  
Fracture Probability ◽  
Focal Plane Arrays ◽  
Thermal Shock Test ◽  
Readout Integrated Circuit ◽  
Three Dimensional Modeling

The square checkerboard buckling deformation appearing in indium antimonide infrared focal-plane arrays (InSb IRFPAs) subjected to the thermal shock tests, results in the fracturing of the InSb chip, which restricts its final yield. In light of the proposed three-dimensional modeling, we proposed the method of thinning a silicon readout integrated circuit (ROIC) to level the uneven top surface of InSb IRFPAs. Simulation results show that when the silicon ROIC is thinned from 300 μm to 20 μm, the maximal displacement in the InSb IRFPAs linearly decreases from 7.115 μm to 0.670 μm in the upward direction, and also decreases linearly from 14.013 μm to 1.612 μm in the downward direction. Once the thickness of the silicon ROIC is less than 50 μm, the square checkerboard buckling deformation distribution presenting in the thicker InSb IRFPAs disappears, and the top surface of the InSb IRFPAs becomes flat. All these findings imply that the thickness of the silicon ROIC determines the degree of deformation in the InSb IRFPAs under a thermal shock test, that the method of thinning a silicon ROIC is suitable for decreasing the fracture probability of the InSb chip, and that this approach improves the reliability of InSb IRFPAs.

scholarly journals A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 813-826
Author(s):  
Farid Uddin Ahmed ◽  
Zarin Tasnim Sandhie ◽  
Liaquat Ali ◽  
Masud H. Chowdhury
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Voltage Regulation ◽  
High Density ◽  
On Chip

Advanced III/V quantum-structure devices for high performance infrared focal plane arrays

2009 ◽  
Author(s):  
Robert Rehm ◽  
Martin Walther ◽  
Johannes Schmitz ◽  
Frank Rutz ◽  
Joachim Fleissner ◽  
...  
Keyword(s):  
Focal Plane ◽  
High Performance ◽  
Focal Plane Arrays ◽  
Quantum Structure ◽  
Infrared Focal Plane Arrays

A Novel Scheme for Wide Bandwidth Chip-to-Chip Communications

2007 ◽  
Vol 4 (1) ◽  
pp. 1-7 ◽  
Author(s):  
Qing Liu ◽  
Patrick Fay ◽  
Gary H. Bernstein
Keyword(s):  
Integrated Circuits ◽  
Coplanar Waveguide ◽  
Impedance Matching ◽  
Three Dimensional ◽  
Fabrication Process ◽  
Silicon Substrates ◽  
Electromagnetic Simulations ◽  
Communication Paradigm ◽  
On Chip ◽  
Test Chips

Quilt Packaging (QP), a novel chip-to-chip communication paradigm for system-in-package integration, is presented. By forming protruding metal nodules along the edges of the chips and interconnecting integrated circuits (ICs) through them, QP offers an approach to ameliorate the I/O speed bottleneck. A fabrication process that includes deep reactive ion etching, electroplating, and chemical-mechanical polishing is demonstrated. As a low-temperature process, it can be easily integrated into a standard IC fabrication process. Three-dimensional electromagnetic simulations of coplanar waveguide QP structures have been performed, and geometries intended to improve impedance matching at the interface between the on-chip interconnects and the chip-to-chip nodule structures were evaluated. Test chips with 100 μm wide nodules were fabricated on silicon substrates, and s-parameters of chip-to-chip interconnects were measured. The insertion loss of the chip-to-chip interconnects was as low as 0.2 dB at 40 GHz. Simulations of 20 μm wide QP structures suggest that the bandwidth of the inter-chip nodules is expected to be above 200 GHz.

Aerosol Jet® Printer as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications

2011 ◽  
Vol 2011 (1) ◽  
pp. 001028-001032
Author(s):  
Michael J. O’Reilly ◽  
Jeff Leal ◽  
Suzette K. Pangrle ◽  
Kenneth Vartanian
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Three Dimensional ◽  
Contact Printing ◽  
Wire Bond ◽  
Printing System ◽  
3D Printed ◽  
Working Distance ◽  
Aerosol Jet Deposition ◽  
Vertical Interconnect

Aerosol Jet deposition systems provide an evolutionary alternative to both wire bond and TSV technology. As part of the Vertical Interconnect Pillar (ViP™) process, the Aerosol Jet system prints high density three-dimensional (3D) interconnects enabling multi-function integrated circuits to be stacked and vertically interconnected in high performance System-in-Packages (SiP). The stacks can include two or more die, with a total height of ∼ 2 millimeters. The non-contact printing system has a working distance of several millimeters above the substrate allowing 3D interconnects to be printed with no Z-height adjustments. The Aerosol Jet printhead is configured with multiple nozzles and a closely coupled atomizer to achieve production throughput of greater than 19,000 interconnects per hour. The Aerosol Jet printer deposits silver fine particle ink to form connections on staggered die stacks. High aspect ratio interconnects, less than 30-microns wide and greater than 6-microns tall, are printed at sub 60-micron pitch. After isothermal sintering at 150° C to 200° C for 30 minutes, highly conductive interconnects near bulk resistivity are produced. Pre-production yields exceeding 80% have been realized. This paper will provide further details on the 3D printed interconnect process, current and planned production throughput levels, and process yield and device reliability status.

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