Interfacial Structure and Evolution in Mesotaxial CoSi2/Si Heterostructure

1991 ◽  
Vol 238 ◽  
Author(s):  
S. R. Hull ◽  
Y. F. Hsieh ◽  
A. E. White ◽  
K. T. Short
Keyword(s):  
High Temperature ◽  
Ion Implantation ◽  
Interfacial Structure ◽  
High Temperature Annealing ◽  
Ripening Process ◽  
Si Substrates ◽  
Buried Layers ◽  
Precipitate Nucleation ◽  
And Control ◽  
First Time

ABSTRACTWe describe the evolution and microstructure of Si/CoSi2/Si (100) and (111) heterostructures formed by Co+ ion implantation into Si substrates (“mesotaxy”), followed by high temperature annealing. It is shown that the CoSi2 precipitate nucleation and ripening process, and eventual coalescence into buried layers, is controlled by interfacial structure and energetics. Understanding and control of these processes allows for the first time synthesis of otherwise almost identical CoSi2 buried layers with either twinned or untwinned CoSi2/Si(111) interfaces.

Structural Relaxation of Amorphous Silicon Induced by High Temperature Annealing

1990 ◽  
Vol 205 ◽  
Author(s):  
L. De Wit ◽  
S. Roorda ◽  
W.C. Sinke ◽  
F.W. Saris ◽  
A.J.M. Berntsen ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
High Temperature ◽  
Ion Implantation ◽  
Amorphous Silicon ◽  
Relaxation Process ◽  
Structural Relaxation ◽  
High Temperature Annealing ◽  
Temperature Range ◽  
Amorphous Si ◽  
Anneal Temperature

Structural relaxation of amorphous Si is studied in the temperature range 500-850 °C using Raman spectroscopy. The minumum value for the Raman peakwidth that can be obtained is inversely proportional to the anneal temperature. The relaxation process is basically the same in a-Si prepared by ion implantation and by vacuum evaporation.

Anisotropic Transformation of 4H-SiC Etching Shapes by High-Temperature Annealing and Its Enhancement by Ion Implantation

2010 ◽  
Vol 49 (4) ◽  
pp. 040203 ◽  
Author(s):  
Yasuyuki Kawada ◽  
Takeshi Tawara ◽  
Shun-ichi Nakamura ◽  
Takashi Tsuji ◽  
Masahide Gotoh ◽  
...  
Keyword(s):  
High Temperature ◽  
Ion Implantation ◽  
High Temperature Annealing

Trench Formation on Ion Implanted SiC Surfaces after Thermal Oxidation

2005 ◽  
Vol 483-485 ◽  
pp. 777-780 ◽  
Author(s):  
Wook Bahng ◽  
Geun Ho Song ◽  
Nam Kyun Kim ◽  
Sang Cheol Kim ◽  
Hyoung Wook Kim ◽  
...  
Keyword(s):  
Growth Rate ◽  
High Temperature ◽  
Ion Implantation ◽  
Doping Concentration ◽  
Side Wall ◽  
Surface Region ◽  
Surface Roughening ◽  
Oxide Growth ◽  
High Temperature Annealing ◽  
Thermal Oxide

The effects of the damage induced during ion implantation on the surface roughening and oxide growth rate were investigated. Using several scheme of doses and acceleration energies, it is found that the amount of the dose predominantly produce damage rather than the acceleration energy, especially near the surface region. It was also found that the damage affects not only the oxide growth rate but also the surface roughening during high temperature annealing. The edge of highly implanted area may have higher doping concentration due to the vicinal side wall effect of the thick oxide mask for ion implantation. It was confirmed by the trench formation after thermal oxide remove.

scholarly journals Diffusion of Dopants and Components in Arsenic-Implanted CdTe/HgCdTe Structures under Different High-Temperature Annealing Conditions

Proceedings ◽  
2019 ◽  
Vol 27 (1) ◽  
pp. 41
Author(s):  
Shi ◽  
Lin ◽  
Wei
Keyword(s):  
High Temperature ◽  
Ion Implantation ◽  
Magnetron Sputtering ◽  
Significant Influence ◽  
Thermal Evaporation ◽  
Layer Structure ◽  
High Temperature Annealing ◽  
Annealing Conditions ◽  
Cap Layer ◽  
Diffusion Behaviors

The CdTe cap layers were grown on CdZnTe-substrated HgCdTe (MCT) LPE epilayers by magnetron sputtering and thermal evaporation. The diffusion behaviors of Cd & Hg components and impurities (As or In) in these CdTe/MCT structures subjected to As ion implantation and various Hg overpressure annealing processes were investigated. The conclusions indicate that the defects at the CdTe/MCT interface could produce the accumulations of impurities and the distributions of induced damages (related to the cap layer structure) have a significant influence on the diffusion of components and impurities. By adjusting annealing procedures, the diffusions of components and impurities can be controlled.

TEM study of buried yttrium silicide formed by ion implantation

1990 ◽  
Vol 48 (4) ◽  
pp. 570-571
Author(s):  
T.L. Alford ◽  
N.D. Theodore ◽  
J.C. Barbour ◽  
C.B. Carter ◽  
J.W. Mayer
Keyword(s):  
Ion Implantation ◽  
Large Scale ◽  
Schottky Barrier Height ◽  
Lattice Mismatch ◽  
Good Thermal Stability ◽  
Si Substrates ◽  
Transmission Electron ◽  
Metal Silicides ◽  
Vacuum Anneal ◽  
Buried Layers

Metal silicides are now used extensively in very-large-scale-integrated (VLSI) electronics due to their low resistivity, good thermal stability, and ability to form on Si. Of these silicides, yttrium silicide, YSi2-x has essentially 0% lattice mismatch with (111)Si, a low Schottky barrier height on n-type Si, and a unit cell based on the AlB2-type structure, but with 15-20% vacancies on the Si sublattice. Recent investigations of high-temperature ion implantation of yttrium ions into Si have emphasized the formation of buried-silicide layers. This study is focussed on the microstructure and defects in the vicinity of buried YSi2-x layers formed by Y-ion implantation into Si.Yttrium-silicide buried layers were formed by implanting 330 or 660 keV Y ions into (11l)Si substrates held at 450°C followed by a 1000°C, 1-hour vacuum anneal. The implant fluences varied from 1 to 3.6×l017 Y/cm2. Cross-section transmission electron microscopy (XTEM) analysis was carried out using a JEOL 4000EX electron microscope operating at 400 kV.

Silicon on Insulator Formed By O+ OR N+ Ion Implantation

1985 ◽  
Vol 53 ◽  
Author(s):  
P.L.F. Hemment
Keyword(s):  
High Temperature ◽  
Ion Implantation ◽  
Silicon On Insulator ◽  
Defect Annealing ◽  
Chemical Segregation ◽  
High Temperature Processing ◽  
Buried Layers

ABSTRACTThe synthesis of buried layers of SiO2 and Si3N4, by ion implantation is reviewed. This process, which may be used to form device worthy silicon-on-insulator (SOI) structures, involves (i) implantation of O+ or N+ ions and (ii) high temperature processing to achieve defect annealing and chemical segregation of the implanted species.

Photoluminescence Studies of Annealed GaAs Films Grown on Si Substrates

1988 ◽  
Vol 116 ◽  
Author(s):  
M. Bugajski ◽  
K. Nauka ◽  
S.J. Rosner ◽  
D. Mars
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Free Carrier ◽  
Apparent Difference ◽  
High Temperature Annealing ◽  
Si Substrates ◽  
Gaas Films ◽  
Excitonic Emission ◽  
Heavily Doped ◽  
Photoluminescence Studies

AbstractLow temperature (T - 5K) photoluminescence (PL) has been measured on a variety of as-grown and annealed GaAs films grown on Si substrates by the MBE technique. The PL spectra of the annealed GaAs layers showed an apparent difference between the nomigally undoped samples with free carrier concentrations below 1015 cm−3 and the layers with dopant concentrations exceeding 1017 atoms cm−3 . The annealing caused an increase of both excitonic and defect related PL intensities in low doped samples. In heavily doped layers the annealing suppressed excitonic emission and strongly enhanced defect related luminescence bands. Observed post annealed infrared shifts of the PL peaks in the excitonic region are explained assuming a tetragonally distorted GaAs lattice under tensile stress, and an increase in stress after high temperature annealing.

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