An Etch-Back Planarization Process Using A Sacrificial Polymide Layer

1991 ◽  
Vol 240 ◽  
Author(s):  
J. R. Lothian ◽  
T. R. Fullowan
Keyword(s):  
Surface Topography ◽  
Dielectric Layer ◽  
Rate Ratio ◽  
Parallel Plate ◽  
Etch Rate ◽  
Dielectric Film ◽  
Sacrificial Layer ◽  
Loading Effect ◽  
Planarization Process ◽  
Etching System

ABSTRACTAn etch-back polymide planarization process for the emitter contact of AlGaAs/GaAs HBTs using PC-1500 is presented. The degree of surface topography has a major impact on the yield in HBT fabrication. A planarization process using a spin-on sacrificial layer to produce a planar interlevel dielectric layer would be very beneficial in allowing thicker and more uniform emitter contacts therefore enhancing the yield and current handling capability. The PC-1500 polymer flows at 200°C and provides a much better planarity than regular photoresist. For patterns from -3 μm to 250 this polymer can achieve 80% to 92% planarity. The wafers were etched in a parallel plate, single wafer reactive ion-etching system with a mixture of oxygen and Freon-14. The etch rate of this polymer increased with the oxygen content of the discharge then became fairly constant at high O2 concentrations while the etch rate of the underlying dielectric film (SiN) was proportional to the Freon 14 content. This new polymer shows little loading effect. A 1:1 etch rate ratio of SiN to PC-1500 was established for good planarity.

The Influence of HBr Discharge Ambience on Poly-Si/SiO2 Etching Selectivity

1991 ◽  
Vol 223 ◽  
Author(s):  
E. Ikawa ◽  
K. Tokashiki ◽  
T. Kikkawa ◽  
Y. Teraoka ◽  
I. Nishiyama
Keyword(s):  
Plasma Etching ◽  
Parallel Plate ◽  
Etch Rate ◽  
Etching Rate ◽  
Mass Analysis ◽  
Ion Etching ◽  
Loading Effect ◽  
Batch Type ◽  
Etching Selectivity ◽  
Hbr Plasma

ABSTRACTThe influence of HBr discharge ambience on SiO2 etching is investigated. A batch type parallel-plate reactive ion etching (RIE) dry etcher was used. The discharge ambience was changed by changing the numbers of poly-Si and SiO2 wafers in the same chamber. It is found that as the number of poly-Si wafers increased, the poly-Si etch rate slightly decreased due to a loading effect and SiO2 etching rate drastically increased. The selectivity of poly-Si / SiO2 decreased with increasing the ratio of the loaded poly-Si number in the same chamber. When A12O3 wafers instead of poly-Si wafers were loaded with SiO2 substrates, SiO2 etching rate enhancement did not occur. Therefore, increase of SiO2 etch rate could not be explained using a loading effect. From the results of mass analysis during etching in Si contained HBr plasma, etching products SiBrx (x=1,2,3) peaks were observed. Namely, when the Si etching products were supplied to SiO2 surface, SiO2 etch rate increased. In order to suppress the enhancement of SiO2 etch rate, the etch temperature must be reduced.

Three Dimensional Bacteria Concentration by Negative Dielectrophoresis

2013 ◽  
Vol 699 ◽  
pp. 251-256
Author(s):  
T. Hisajima ◽  
L. Mao ◽  
K. Shinzato ◽  
M. Nakano ◽  
J. Suehiro
Keyword(s):  
Escherichia Coli ◽  
Numerical Simulation ◽  
Dielectric Layer ◽  
Parallel Plate ◽  
Three Dimensional ◽  
Three Dimension ◽  
Escherichia Coli Cells ◽  
Opposite Electrode ◽  
Novel Method ◽  
Thin Dielectric Layer

Thispaper reports a novel method to concentrate bacteria in three-dimension by negative dielectrophoretic (n-DEP) force in a microchannel. This was achieved by placing a thin dielectric layer on one of a pair of parallel plate electrodes. The dielectric layer having a home-plate like pentagonal shape, forms a gradient of electric field causing n-DEP. A three-dimensional numerical simulation of bacteria trajectory predicts that bacteria flowing a microchannel were three-dimensionally concentrated beneath the tip of the pentagonal dielectric thin layer. The trajectory and concentration of bacteria under n-DEP force were also experimentally confirmed using Escherichia coli cells. Bacteria moved along edges of the dielectric layer and were pushed to the opposite electrode, resulting in their concentration in three-dimension. The proposed device might be applicable to selective concentration of bacteria depending on their dielectric properties.

A method for increasing the etch‐rate ratio of oxides to nonoxides in inert‐gas ion milling processes

1980 ◽  
Vol 51 (6) ◽  
pp. 3362-3364 ◽  
Author(s):  
U. Gerlach‐Meyer ◽  
J. W. Coburn ◽  
E. Kay
Keyword(s):  
Rate Ratio ◽  
Etch Rate ◽  
Inert Gas ◽  
Ion Milling

Novel Measurement Technique on 3D Surface Topography of Polishing Pad

2008 ◽  
Vol 53-54 ◽  
pp. 265-272
Author(s):  
Dong Ming Guo ◽  
N. Qin ◽  
Ren Ke Kang ◽  
Zhu Ji Jin
Keyword(s):  
Surface Topography ◽  
Chemical Mechanical Planarization ◽  
Sampling Interval ◽  
3D Measurement ◽  
Sampling Area ◽  
Polishing Pad ◽  
3D Surface ◽  
3D Surface Topography ◽  
Planarization Process ◽  
Polishing Pads

Among the properties of polishing pad, the surface roughness plays a crucial role in CMP (Chemical Mechanical Planarization) process. However, there is no acknowledged standard for measuring and characterizing the roughness of pad surface in 3D measurement. In this paper Talysurf CLI 2000 working on the principle of dynamic confocal measurement was initially suggested to measure the 3D surface topography of polishing pads through theoretical and experimental analysis. In addition, based on the Nyquist folding frequency and the statistical theory, a selection technique for sampling interval and sampling area was proposed and verified through experiments. The results showed that Talysurf CLI 2000 is more suitable than NewView to measure the 3D surface topography of polishing pads. 2μm sampling interval, 0.5×0.5mm2 sampling area and 10μm interval, 1×1mm2 area are respectively recommended for IC1000/SubaIV and SubaIV polishing pad.

Single Wafer, Anisotropic Etching of Polysilicon with C12/SF6 and Trielectrode Reactor Operation

1986 ◽  
Vol 68 ◽  
Author(s):  
James E. Nulty
Keyword(s):  
Bias Voltage ◽  
Etch Rate ◽  
Proximity Effects ◽  
The Self ◽  
Rf Power ◽  
Reactor Operation ◽  
Lower Electrode ◽  
Dc Bias ◽  
Bias Versus ◽  
Etching System

AbstractA totally anisotropic, highly selective dry poly etch process has been developed that is capable of etching sub-2.0 micron linewidths.Doped poly etch rates of 10,000 A/min.are obtained using C12-only chemistry.Standard novolac or bilevel photoresist is used, depending on the lithography requirements.Anisotropy is achieved without the use of carbon-containing gases; as a result, minimal proximity effects are observed between dense and stand alone etched lines.Wafer maps of etched linewidths on 4-inch wafers are presented, showing mask to final bias and uniformity results.A commercially available triode dry etching system was used for the work.The self-induced dc bias voltage can be selected regardless of the applied rf power.The effect of variable self-induced dc bias versus applied rf power is presented for selectivity, upper and lower electrode interactions, and etch rate uniformity.Characterization by the use of spectroscopy is also presented, showing changes due to varying the self-induced dc bias at a constant rf power.

Study of the Pull-In Voltage for MEMS Parallel Plate Capacitor Actuators

2003 ◽  
Vol 782 ◽  
Author(s):  
Emmanuel Saucedo-Flores ◽  
Rubén Ruelas ◽  
Martín Flores ◽  
Jung-chih Chiao
Keyword(s):  
Dielectric Layer ◽  
Parallel Plate ◽  
Electrode Position ◽  
Design Decision ◽  
Significant Finding ◽  
Parallel Plate Capacitor ◽  
Softening Effect ◽  
Plate Capacitor ◽  
Electrode Displacement ◽  
The Impact

ABSTRACTThis paper provides new investigation for the static and dynamic behavior of a MEMS parallel plate capacitor derived by analytical and numerical design modeling programs developed in Matlab. One significant finding is about the role, which has so far overlooked in many analyses, of a dielectric layer normally placed on top of the ground electrode to avoid short circuiting risks. It is demonstrated in this paper that this layer produces an increased force between electrodes that in turns decreases the well-known pull-in voltage, Vpi, as compared to the one calculated when this dielectric layer is not considered on the system's static analysis. Expressions for the static Vpi and its corresponding maximum stable electrode swing xpi are derived to take the above effect into account.The system dynamic analysis is done with a user-friendly Simulink interface constructed to allow easy introduction of capacitor design dimensions, material parameter values and voltage signal stimuli. The impact of any combination of these parameters on the electro-mechanical system behavior, that is, the voltage-electrode position dependence data can be easily extracted and become of help for design decision making on the early design stages of this type of structures. This modeling tool interface is based on solving the full differential equation that describes the free electrode displacement without relying on linearizing the inverse quadratic electrode separation dependence of the electro-static force term. This approach intrinsically takes into account the voltage dependant k-spring softening effect derived precisely from a linearizing simplification. Finally, by applying a saw-tooth voltage waveform, the dynamic pull-in voltage and the maximum stable electrode travel range are observed to go well beyond the predicted static pull-in voltage and travel range values.

Organic thin film transistors with novel photosensitive polyurethane as dielectric layer

RSC Advances ◽  
2016 ◽  
Vol 6 (7) ◽  
pp. 5377-5383 ◽  
Author(s):  
Yao Li ◽  
He Wang ◽  
Xuehui Zhang ◽  
Qiong Zhang ◽  
Xuesong Wang ◽  
...  
Keyword(s):  
Thin Film ◽  
Dielectric Layer ◽  
Thin Film Transistors ◽  
Dielectric Film ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Promising Candidate ◽  
Solution Processable

The solution-processable photosensitive polyurethane dielectric film is a promising candidate for the exploration of organic thin-film transistors (OTFTs).

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