Photoluminescence of Extended Defects in Silicon-on-Insulator Formed by Implantation of Oxygen

1995 ◽  
Vol 378 ◽  
Author(s):  
Y. H. Qian ◽  
J. H. Evans ◽  
L. F. Giles ◽  
A. Nejim ◽  
P. L. F. Hemment
Keyword(s):  
High Temperature ◽  
Optical Activity ◽  
Stacking Faults ◽  
Silicon On Insulator ◽  
Threading Dislocations ◽  
Extended Defects ◽  
High Temperature Annealing ◽  
Stacking Fault Tetrahedra ◽  
Before And After ◽  
Dislocation Related Luminescence

AbstractPL and TEM have been carried out on SIMOX structures before and after thinning the silicon overlayer by a process of sacrificial oxidation. The implantation and high temperature annealing schedules involved in fabricating SIMOX material result in threading dislocations and stacking fault tetrahedra and pyramidals in the silicon overlayer. The optical activity of these extended defects is found to be low. However, after the sacrificial oxidation, strong dislocation related luminescence is observed, which is attributed to the presence of oxidation-induced stacking faults now present in the overlayer.

Observation of Shrinking and Reformation of Shockley Stacking Faults by PL Mapping

2006 ◽  
Vol 527-529 ◽  
pp. 375-378 ◽  
Author(s):  
Toshiyuki Miyanagi ◽  
Hidekazu Tsuchida ◽  
Isaho Kamata ◽  
Tomonori Nakamura ◽  
R. Ishii ◽  
...  
Keyword(s):  
High Temperature ◽  
Laser Irradiation ◽  
High Power ◽  
Stacking Faults ◽  
High Temperature Annealing ◽  
High Power Laser ◽  
Power Laser ◽  
Before And After ◽  
Basal Plane Dislocation ◽  
Pl Mapping

We provide evidence of shrinking of Shockley-type stacking faults (SSFs) in the SiC epitaxial layer by high temperature annealing. Photoluminescence (PL) mapping in combination with high-power laser irradiation makes it possible to investigate the formation of SSFs, which lie between a pair of partial dislocations formed by dissociation of a basal plane dislocation (BPD), without fabrication of pin diodes. Using this technique, we investigated the annealing effect on SSFs. Comparing before and after annealing at 600°C for 10 min, it became obvious that high-temperature annealing results in shrinking of the faulted area of the SSFs. The SSFs form into the same features as those before annealing when high-power laser irradiation is performed again on the same area. This result shows that the faulted area of SSFs shrinks by 600°C annealing but the nuclei of SSFs (BPDs) do not disappear.

Defect reduction in oxygen implanted silicon-on-insulator material during high-temperature annealing

1989 ◽  
Vol 47 ◽  
pp. 604-605
Author(s):  
P. Roitman ◽  
B. Cordts ◽  
S. Visitserngtrakul ◽  
S.J. Krause
Keyword(s):  
High Temperature ◽  
Annealing Temperature ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Current ◽  
Defect Reduction ◽  
Annealing Step ◽  
Multiple Cycle ◽  
Defect Densities

Synthesis of a thin, buried dielectric layer to form a silicon-on-insulator (SOI) material by high dose oxygen implantation (SIMOX – Separation by IMplanted Oxygen) is becoming an important technology due to the advent of high current (200 mA) oxygen implanters. Recently, reductions in defect densities from 109 cm−2 down to 107 cm−2 or less have been reported. They were achieved with a final high temperature annealing step (1300°C – 1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. However, the processes and conditions for reduction and elimination of precipitates and defects during high temperature annealing are not well understood. In this work we have studied the effect of annealing temperature on defect and precipitate reduction for SIMOX samples which were processed first with high temperature, high current implantation followed by high temperature annealing.

Suppression of SiC surface roughening during high-temperature annealing by atmospheric control using purified Ar gas

2010 ◽  
Vol 25 (4) ◽  
pp. 708-710 ◽  
Author(s):  
Atsushi Ogura ◽  
Daisuke Kosemura ◽  
Shingo Kinoshita
Keyword(s):  
Surface Roughness ◽  
High Temperature ◽  
Surface Roughening ◽  
Annealing Atmosphere ◽  
High Temperature Annealing ◽  
Force Microscopy ◽  
Atomic Force ◽  
Before And After ◽  
Furnace Tube ◽  
Ar Gas

4H-silicon carbide (SiC) wafers were annealed at 1300 and 1600 °C for 30 min and 60 min in a conventional and purified Ar atmosphere. The surface roughness before and after annealing was evaluated by atomic force microscopy. The surface roughness before annealing was approximately 2.37 nm in root mean square. The roughness, after annealing for 30 min at 1300 and 1600 °C in a conventional Ar furnace, was increased to 4.53 and 14.9 nm, respectively. The roughness, after annealing for 60 min, was 5.01 and 19.1 nm, respectively. In this study, the G3 grade Ar gas (99.999%) was supplied in the conventional furnace tube. When the Ar gas was purified to an impurity concentration of less than 1 ppb, and it was supplied in the leak-tight furnace tube, the roughness after 30-min annealing improved 4.27 and 6.93 nm at 1300 and 1600 °C, respectively. The roughness after 60-min annealing was also reduced to 3.54 and 9.28 nm, respectively. We assume that a significant reduction of H2O concentration in the annealing atmosphere might play an important role in suppressing surface roughening of SiC during high-temperature annealing.

Formation and Properties of Schottky Diodes on 4H-SiC after High Temperature Annealing with Graphite Encapsulation

2006 ◽  
Vol 527-529 ◽  
pp. 915-918 ◽  
Author(s):  
Y. Wang ◽  
M.K. Mikhov ◽  
B.J. Skromme
Keyword(s):  
High Temperature ◽  
Ideality Factor ◽  
Schottky Diodes ◽  
Extended Defects ◽  
High Temperature Annealing ◽  
Force Microscopy ◽  
Atomic Force ◽  
Current Voltage ◽  
Encapsulation Method ◽  
The Impact

The impact of high temperature annealing using graphite encapsulation (formed by baking photoresist) on the electrical properties of Ni Schottky diodes formed on the annealed surfaces is studied. The surface morphology is also characterized by atomic force microscopy (AFM). Annealing for 10 minutes at temperatures up to 1800 °C with graphite encapsulation actually reduces the high-current ideality factor of the diodes while raising the current-voltage barrier height (linearly extrapolated to unity ideality factor) from 1.453 V to 1.67-1.73 V. Excess leakage current occurs only in a subset of diodes, which are believed to be affected by extended defects. The AFM images show no significant surface roughening, and the graphite can be removed after processing. This encapsulation method is found to be highly effective in preserving the electronic properties of the surface during high temperature annealing.

Formation of stacking-fault tetrahedra in low defect density oxygen-implanted silicon-on-insulator material

1992 ◽  
Vol 50 (2) ◽  
pp. 1402-1403
Author(s):  
June-Dong Lee ◽  
Stephen Krause ◽  
Peter Roitman
Keyword(s):  
Integrated Circuits ◽  
Defect Density ◽  
Silicon Layer ◽  
Stacking Fault ◽  
Silicon On Insulator ◽  
Threading Dislocations ◽  
Annealing Conditions ◽  
Stacking Fault Tetrahedra ◽  
Higher Temperature ◽  
Defect Densities

Fabrication of integrated circuits on SOI (Silicon-On-Insulator) material is very attractive because it offers high component density, immunity to latch-up and radiation hardness. Among various SOI techniques SIMOX Separation by IMplantation of OXygen) provides the best material, with carrier mobilities and defect densities approaching bulk silicon values, Early SIMOX wafers were implanted at temperatures below 600°C and annealed at high temperature (>1300°C), which gave a high defect density (109cm−2), including threading dislocations and narrow stacking faults (SFs), as shown in Figure 1. Higher temperature (>600°C) implantation of SIMOX reduced defect densities to 106cm-2 with pairs of narrow SFs in the top silicon layer, as shown in Figure 2. This paper describes a further reduction of defect density in SIMOX material through various annealing conditions, which has resulted in a defect density less than 105cm−2. A new formation mechanism for stacking fault tetrahedra is also discussed.Silicon (100) wafers were sequentially implanted (620°C) and annealed (at 1320°C for 5 hours) to doses of 0.5, 0.5, and 0.8×l018cm-2.

High Temperature Annealing SP-AlN Ameliorates the Crystal Quality ofAl0.5Ga0.5N Regrowth

2020 ◽  
Vol 1014 ◽  
pp. 14-21
Author(s):  
Wen Kai Yue ◽  
Zhi Min Li ◽  
Xiao Wei Zhou ◽  
Jin Xing Wu ◽  
Pei Xian Li
Keyword(s):  
Raman Spectroscopy ◽  
High Temperature ◽  
Annealing Process ◽  
High Temperature Annealing ◽  
High Quality ◽  
Rocking Curve ◽  
Stress Mode ◽  
Aln Film ◽  
Before And After ◽  
Screw Dislocation Density

In this study, the effect of a high-temperature annealing process on AlN is investigated. The high-temperature annealing process reduces the screw dislocation density of the AlN film to 2.1x107 cm-2. The AlN surface is highly flat. Through HRXRD and Raman spectroscopy, the stress mode changes in the sputtered AlN film before and after high-temperature annealing were studied in depth. Based on the HTA-AlN template, a high-quality, high-Al composition AlGaN epitaxial wafer, with a (0002) plane rocking curve FWHM of 246 arcsec , was prepared at 1080°C The growth mode of AlGaN grown directly on the AlN template at low temperature is summarized.

High-Quality SOI by Oxygen Implantation into Silicon

1987 ◽  
Vol 93 ◽  
Author(s):  
A. H. van Ommen ◽  
H. J. Ligthart ◽  
J. Politiek ◽  
M. P. A. Viegers
Keyword(s):  
High Temperature ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Quality ◽  
Cubic Symmetry ◽  
Buried Oxide ◽  
Simple Cubic ◽  
Precipitate Growth

ABSTRACTHigh quality Silicon-On-Insulator, with a dislocation density lower than 105cm−2, has been formed by high temperature annealing of high-dose oxygen implanted silicon. In the as-implanted state, oxygen was found to form precipitates in the top silicon film. In the upper region these precipitates were found to order into a superlattice of simple cubic symmetry. Near the interface with the buried oxide film the precipitates are larger and no ordering occurs in that region. Contrary to implants without precipitate ordering where dislocations are observed across the entire layer thickness of the top silicon film, dislocations are now only found near the buried oxide. The precipitate ordering appears to prevent the dislocations to climb to the surface. High temperature annealing results in precipitate growth in this region whereas they dissolve elsewhere. These growing precipitates pin the dislocations and elimination of precipitates and dislocations occurs simultaneously, resulting in good quality SOI material.

Influence of High Temperature Annealing in Nitrogen on Upconversion Luminescence of β-NaYF4: Yb3+, Er3+ Hexagonal Sub-Microplates

2012 ◽  
Vol 496 ◽  
pp. 79-83
Author(s):  
Jun Wei Zhao ◽  
Tie Kun Jia ◽  
Xiang Gui Kong
Keyword(s):  
High Temperature ◽  
Sodium Citrate ◽  
Hexagonal Phase ◽  
Upconversion Luminescence ◽  
Annealing Treatment ◽  
Annealing Process ◽  
High Temperature Annealing ◽  
Nonradiative Relaxation ◽  
Before And After ◽  
Hydrothermal Methods

The pure β-NaYF4: Yb3+, Er3+ hexagonal sub-microplates were successfully prepared by the combination of coprecipitation and hydrothermal methods using sodium citrate as chelator. The size of them is about 600 nm × 400 nm (side length × thickness). The obtained sample was divided into two parts and one of them was annealed in nitrogen at 300 °C for 2 hours. The crystal structure of the β-NaYF4: Yb3+, Er3+ hexagonal sub-microplates before and after annealing treatment is hexagonal phase. Under the excitation of 980 nm diode laser, the upconversion luminescence intensity the sample after annealing is much stronger than that of the sample without annealing treatment. High temperature annealing process improved the crystallization of the sample, resulting in the decrease of the nonradiative relaxation and the enhancement of the upconversion luminescence.

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