Individual forecasting of reliability of bipolar transistors by using electrical voltage as a simulation factor

Individual forecasting of the reliability of semiconductor devices, taking into account gradual failures, is an urgent task, as it allows you to choose highly reliable instances for critical electronic devices of long-term functioning. In relation to bipolar transistors, an approach is proposed that allows us to solve this problem by using the voltage applied to the collector-emitter junction as a simulated effect. Using the example of highpower bipolar transistors of the KT872A type, it is shown how the problem is solved. For the sample of transistors of this type using the results of a training experiment, two equations were obtained to describe the electrical parameter under consideration (a static base current transfer coefficient in a circuit with a common emitter), the value of which judges the absence or presence of a gradual failure for a specific instance. The first equation shows how the electrical parameter changes on average depending on the voltage applied to the collector – emitter junction. The second equation describes the average degradation of the electrical parameter during long-term operating time of transistors. Based on these two equations, a simulation model of the reliability of bipolar transistors of the type in question is obtained in the form of a communication function that shows what level of simulation voltage corresponds to a given operating time. As applied to the transistors of the type under consideration, the obtained simulation model allows us to individually predict reliability by the gradual failures of the same type of samples that did not participate in the training experiment. To do this, first determine the value of the simulation voltage corresponding to a given operating time. This is achieved by substituting a given operating time into the model. The individual forecasting of the reliability of a new onetype instance consists in measuring the electrical parameter of this instance at a voltage on the transistor collector corresponding to the calculated simulation value, and comparing the measurement result with the norm set on the electrical parameter.

Effect of Hole Extraction from the Base Region of a Silicon p–n–p Transistor on its Reactive Impedance

Transistor structures are the basic elements of integrated circuitry and are often used to create not only transistors themselves, but also diodes, resistors, and capacitors. Determining the mechanism of the occurrence of inductive type impedance in semiconductor structures is an urgent task, the solution of which will create the prerequisites for the development of solid-state analogs of inductors. The purpose of the work is to establish the effect of extraction of non-equilibrium charge carriers from the base region on the reactive impedance of a bipolar p–n–p transistor.Using impedance spectroscopy in the frequency range 20 Hz–30 MHz, the structures based on p–n–p transistors KT814G manufactured by JSC “INTEGRAL” were studied. It is shown that in the transistor structures it is possible to observe the “effect of negative capacitance” (inductive type impedance). It is established that the most probable cause of the inductive type impedance is the accumulation of uncompensated charge of holes in the base, the value of inductive impedance is influenced by both the injection efficiency in the base–emitter junction and the extraction efficiency in the base–collector junction.The results can be applied in the elaboration of technologies for the formation of elements of silicon based integrated circuits with an impedance of inductive type.

Design and Technology Analysis Bipolar Transistors Based on High Performance Structures AlGaAs / GaAs Structures for Submicron LargeIntegrated Circuits

This paper analyzes performance of bipolar transistors based on AlGaAs/GaAs heterostructures (HBT). Use of heterojunction as emitter junction allows radical improvement of its performance. Numerical simulation of HBT in ring oscillator mode showed that the delay of the BT with 1x2 µm emitter can be reduced to 8 ps at a maximum current of 105 A/cm2. HBT with one and two (emitter and collector) heterojunctions showed 24 ps delay at 9.1 mW and 17 ps at 40 mW.

Research on Characteristics of the Photovoltaic Cells Integrated on Chip

The influence factors of Photovoltaic (PV) cells characteristics integrated on chip were analyzed based on the fabrication process and the structure of the PV cells and CMOS devices. The results show the substrate doping concentration, the emitter doping concentration, the emitter junction depth and the thickness of device layer directly determine the conversion efficiency, open voltage and the light-generated current of photovoltaic cells. In the emitter doping concentration range of 1×1019/cm3 to 1×1021/cm3 and the substrate doping concentration range of 1.0×1015/cm3 to 1.0×1017/cm3, the Photovoltaic cells have batter conversion characteristics. The PV cells were designed based on the analysis results in PC1D, and the conversion efficiency is 9.43%. The Photovoltaic cells and the CMOS devices have batter fabrication technology compatibility integrated on chip.

Comparison of Total Losses of 1.2 kV SiC JFET and BJT in DC-DC Converter Including Gate Driver

The 1.2 kV SiC JFET and BJT devices have been investigated and compared with respect to total losses including the gate driver losses in a DC-DC converter configuration. The buried grid, Normally-on JFET devices with threshold voltage of -50 V and -10V are compared to BJT devices with ideal semiconductor and passivating insulator interface and an interface with surface recombination velocity of 4.5•104 cm/s yielding agreement to the reported experimental current gain values. The conduction losses of both types of devices are independent of the switching frequency while the switching losses are proportional to the switching frequency. The driver losses are proportional to the switching frequency in the JFET case but to a large extent independent of the switching frequency in the BJT case. The passivation of the emitter junction modeled here by surface recombination velocity has a significant impact on conduction losses and gate driver losses in the investigated BJT devices.

Improved Current Gain in GaN/SiC Heterojunction Bipolar Transistors by Insertion of Ultra-Thin AlN Layer at Emitter-Junction

GaN/SiC Heterojunction Bipolar Transistors (HBTs) with ultra-thin AlN insertion layers at the n-GaN/p-SiC emitter junction are proposed to improve carrier injection efficiency. The current-voltage characteristics of n-GaN/AlN/p-SiC heterojunctions have exhibited very small reverse leakage and good rectification. The capacitance-voltage measurement have revealed that the conduction band offset between n-GaN and p-SiC has been reduced from -0.74 eV to -0.54 eV by insertion of AlN, indicating that the GaN/AlN/SiC heterojunction may show better electron-injection efficiency. A significantly improved common-base current gain (α~0.2) is obtained for GaN/AlN/SiC HBTs with initial N* pre-irradiation, while it was very low (α~0.001) for GaN/SiC HBTs without AlN layers.