Effect of N+ Ion Implantation and Gox Process on in and B Channel Profile

2000 ◽  
Vol 610 ◽  
Author(s):  
G. Curello ◽  
R. Rengarajan ◽  
J. Faul ◽  
H. Wurzer ◽  
J. Amon ◽  
...  

AbstractIn this work, we report on the effect of different dual gate oxide (DGox) processes on the electrical properties of CMOS devices in deep submicron embedded DRAM (eDRAM) technology. Also discussed, is the effect of N+ Ion Implantation on the diffusion / segregation behaviour of B and In channel dopants. In particular, it will be shown that the N+ dose required to obtain a certain combination of dual gate oxide thickness varies with the gate oxide process. Effects of N+ dose on the In and B channel profiles are studied using SIMS. The impact of “thickness-equivalent” DGox processes on short channel effect (SCE) and carrier mobility is analyzed and tradeoffs for optimization of device performances are discussed.

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Satyam Shukla ◽  
Sandeep Singh Gill ◽  
Navneet Kaur ◽  
H. S. Jatana ◽  
Varun Nehru

Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (Ion/Ioff), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.


2009 ◽  
Vol 95 (3) ◽  
pp. 033507 ◽  
Author(s):  
A. Valletta ◽  
P. Gaucci ◽  
L. Mariucci ◽  
A. Pecora ◽  
M. Cuscunà ◽  
...  

2005 ◽  
Vol 108-109 ◽  
pp. 637-642 ◽  
Author(s):  
Domenico Mello ◽  
Francesco Cordiano ◽  
Andrea Gerosa ◽  
Margherita Padalino ◽  
Carmelo Gagliano ◽  
...  

Contamination controls are very important issues in microelectronics. Any wrong substance introduction in process chambers can cause damages to the production line. Therefore, an extensive control is important because every operation in the process flow (also the most insignificant) can become fatal for the correct functioning of a microelectronic device. The aim of this work is to evaluate the impact of small metallic contamination in the range of 1011÷1012 at/cm2 on silicon substrates implanted with different ion species (As, B and P). An important example of failure related to metallic contamination in a wet bench is reported in this work. The problem appears in a particular class of flash memory devices processing. The electrical parametric test shows a wrong gate oxide thickness and Qbd values out of range, confirmed by early breakdown events and anomalous C-V characteristics. The cause of the failure is morphologically identified off-line by using TEM: the cross section shows a wrong gate oxide thickness and an anomalous interface between gate oxide and silicon substrate. It appears clear that the root failure cause is related to the ion implantation (As in this case) and to the cleaning before gate oxide growth. A short process flow was performed and analyzed step by step in order to identify the failure cause. Many different analytical techniques have been used for each step and all of these provide consistent results. In particular TXRF analysis on wafers processed immediately after cleaning do not show any contamination while Cu and Fe contaminants are observed after sample oxidation and As implant. Metallic contaminants are captured by the substrate after it is implanted with As, and the following RCA cleaning is not able to remove them. In addition, the presence of these metallic contaminants induces roughness of the Si surface and the growth of gate oxide is not controlled (faster oxidation). If different substrates are used, e.g. silicon implanted with B or un-implanted, this contamination level is not detected and does not lead to oxide reliability problems. Once the mechanism of metal contaminant interaction with dopant is identified the introduction of an in-line monitoring is possible, thus allowing to prevent the device failure. The short process loop can be considered as a good method to prepare the substrate before TXRF analysis. After this study the monitor has been integrated in the production line controls


2020 ◽  
Vol 116 (16) ◽  
pp. 162106 ◽  
Author(s):  
N. Lee ◽  
R. Tsuchiya ◽  
G. Shinkai ◽  
Y. Kanno ◽  
T. Mine ◽  
...  

2019 ◽  
Vol 9 (1) ◽  
pp. 305-311
Author(s):  
Paula G. Der Agopian ◽  
Joao A. Martino ◽  
E. Simoen ◽  
C. Claeys

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