Grain Size and Chemical Composition Effects on the Grain Boundary Resistance of Ceria

2002 ◽  
Vol 730 ◽  
Author(s):  
Xiao-Dong Zhou ◽  
Harlan U. Anderson ◽  
Wayne Huebner

AbstractStudies related to the effects of grain size (30nm – 5.0μm) on the electrical conductivity of undoped CeO2 and Ce0.90Gd0.10O1.95 were performed. A series of impedance spectra as a function of temperature and grain size were analyzed. It was found that the ratio of the grain boundary resistance to the total resistance became lower with decreasing grain size, increasing temperature or increasing Gd content. For the case of Gd doped CeO2, the source of the grain boundary resistance may be due to the trapping of oxygen ions in the grain boundary area.

2011 ◽  
Vol 50 (2) ◽  
pp. 647-655 ◽  
Author(s):  
Tania Pannu ◽  
Kanwar Gulsher Singh Pannu ◽  
Venkataraman Thangadurai

Materials ◽  
2019 ◽  
Vol 12 (3) ◽  
pp. 339 ◽  
Author(s):  
Yong Wang ◽  
Jinguo Wang ◽  
Haohao Zou ◽  
Yutong Wang ◽  
Xu Ran

Cu-2.4 wt.%V nanocomposite has been prepared by mechanical alloy and vacuum hot-pressed sintering technology. The composites were sintered at 800 °C, 850 °C, 900 °C, and 950 °C respectively. The microstructure and properties of composites were investigated. The results show that the Cu-2.4 wt.%V composite presents high strength and high electrical conductivity. The composite sintered at 900 °C has a microhardness of 205 HV, a yield strength of 404.41 MPa, and an electrical conductivity of 79.5% International Annealed Copper Standard (IACS); the microhardness and yield strength reduce gradually with the increasing consolidation temperature, which is mainly due to the growth of copper grain size. After sintering, copper grain size and V nanoparticle both maintain in nanoscale; the strengthening mechanism is related to grain boundary strengthening and dispersion strengthening, while the grain boundary strengthening mechanism plays the most important role. This study indicates that the addition of small amounts of V element could enhance the copper matrix markedly with the little sacrifice of electrical conductivity.


Author(s):  
Mihails Kusnezoff ◽  
Dörte Wagner ◽  
Jochen Schilm ◽  
Christian Heubner ◽  
Björn Matthey ◽  
...  

AbstractCrystallization of highly ionic conductive N5 (Na5YSi4O12) phase from melted Na3+3x-1Y1-xPySi3-yO9 parent glass provides an attractive pathway for cost-effective manufacturing of Na-ion conducting thin electrolyte substrates. The temperature-dependent crystallization of parent glass results in several crystalline phases in the microstructure (N3 (Na3YSi2O7), N5 and N8 (Na8.1Y Si6O18) phases) as well as in rest glass phase with temperature dependent viscosity. The electrical properties of dense parent glass and of compositions densified and crystallized at 700 °C, 800 °C, 900 °C, 1000 °C, and 1100 °C are investigated by impedance spectroscopy and linked to their microstructure and crystalline phase content determined by Rietveld refinement. The parent glass has high isolation resistance and predominantly electrons as charge carriers. For sintering at ≥ 900 °C, sufficient N5 phase content is formed to exceed the percolation limit and form ion-conducting pathways. At the same time, the highest content of crystalline phase and the lowest grain boundary resistance are observed. Further increase of the sintering temperature leads to a decrease of the grain resistance and an increase of grain boundary resistance. The grain boundary resistance increases remarkably for samples sintered at 1100 °C due to softening of the residual glass phase and wetting of the grain boundaries. The conductivity of fully crystallized N5 phase (grain conductivity) is calculated from thorough impedance spectra analysis using its volume content estimated from Rietveld analysis, density measurements and assuming reasonable tortuosity to 2.8 10−3 S cm−1 at room temperature. The excellent conductivity and easy processing demonstrate the great potential for the use of this phase in the preparation of solid-state sodium electrolytes.


2011 ◽  
Vol 172-174 ◽  
pp. 1128-1133 ◽  
Author(s):  
Eric A. Jägle ◽  
Eric J. Mittemeijer

The kinetics of phase transformations for which nucleation occurs on parent-micro-structure grain boundaries, and the resulting microstructures, were investigated by means ofgeometric simulations. The influences of parent microstructure grain-boundary area density,parent grain-size distribution and parent→product kinetics were analysed. Additionally, thesimulated kinetics were compared with predictions from two kinetic models, namely a modelproposed for spatially random nucleation and a model proposed for grain-boundary nucleation.It was found that the simulated transformed fraction as function of time lies in between the twomodel predictions for all investigated parent microstructures and parent→product kinetics.


2011 ◽  
Vol 687 ◽  
pp. 375-379 ◽  
Author(s):  
Hong Tao Yu ◽  
Wen Bo Zhang ◽  
Jing Song Liu ◽  
Han Xing Liu

The dielectric properties of Zr substituted CaCu3Ti4O12ceramics have been investigated in detail. Grain size decreases with Zr content increasing. The hetero-electrical microstructures of prepared samples have been confirmed by the impedance spectra. The dielectric loss has been improved by Zr doping because of the enhancement of grain boundary resistivity. A Debye-like boundary relaxation behavior has been observed in the temperature range of 220-600K. As Zr content increases, the relaxation time increases due to the higher grain boundary concentration. This work has provided an additional proof for the origin of giant dielectric response in CaCu3Ti4O12ceramics.


2017 ◽  
Vol 5 (40) ◽  
pp. 21491-21504 ◽  
Author(s):  
Asma Sharafi ◽  
Catherine G. Haslam ◽  
Robert D. Kerns ◽  
Jeff Wolfenstine ◽  
Jeff Sakamoto

The strong correlation between LLZO grain size and the Li–LLZO stability as a function of Li plating rate is demonstrated. The increase in grain size reduces the grain boundary area and hence the number of possible failure points leading to an increased maximum tolerable current density.


2021 ◽  
Vol 67 (2 Mar-Apr) ◽  
pp. 263
Author(s):  
T. O. Daniel ◽  
U. E. Uno ◽  
K. U. Isah ◽  
U. Ahmadu

This study is focused on the investigation of SnS thin film for transistor application. Electron trap which is associated with grain boundary effect affects the electrical conductivity of SnS semiconductor thin film thereby militating the attainment of the threshold voltage required for transistor operation. Grain size and grain boundary is a function of a semiconductor’s thickness. SnS semiconductor thin films of 0.20, 0.25, 0.30, 0.35, 0.40 μm were deposited using aerosol assisted chemical vapour deposition on glass substrates. Profilometry, Scanning electron microscope, Energy dispersive X-ray spectroscopy and hall measurement were used to characterise the composition, microstructure and electrical properties of the SnS thin film.  SnS thin films were found to consist of Sn and S elements whose composition varied with increase in thickness. The film conductivity was found to vary with grain size and grain boundary which is a function of the film thickness. The SnS film of 0.4 μm thickness shows optimal grain growth with a grain size of 130.31 nm signifying an optimum for the as deposited SnS films as the larger grains reduces the number of grain boundaries and charge trap density which allows charge carriers to move freely in the lattice thereby causing a reduction in resistivity and increase in conductivity of the films which is essential in obtaining the threshold voltage for a transistor semiconductor channel layer operation. The carrier concentration of due to low resistivity of 3.612 ×105 Ωcm of 0.4 μm SnS thin film thickness is optimum and favours the attainment of the threshold voltage for a field effect transistor operation hence the application of SnS thin film as a semiconductor channel layer in a field effect transistor.


2004 ◽  
Vol 835 ◽  
Author(s):  
V. Petrovsky ◽  
P. Jasinski ◽  
H.U. Anderson ◽  
T. Petrovsky

ABSTRACTThe influence of the grain boundaries on the ionic conductivity of yttrium stabilized zirconia (YSZ) was investigated. The initially nanocrystalline samples were prepared using a tape casting process. The samples were annealed at different temperatures in the range from 1000 to 1400°C to overlap the grain size from 100nm to ∼10μm and investigated using impedance spectroscopy. Two distinct semicircles were found on all YSZ samples corresponding to the influence of the grain and grain boundary on the resistance. The activation energies for both resistances are very close (1.00 and 1.03eV correspondingly). The grain resistance does not change significantly during the annealing process, but the grain boundary resistance decreases after high temperature annealing which causes a decrease in the overall resistance of the material. The calculations show that the decrease in the grain boundary resistance is connected only with the increase in the grain size and the specific grain boundary resistance (per unit surface area of grain boundary) does not change with annealing.


1995 ◽  
Vol 400 ◽  
Author(s):  
E.B. Lavik ◽  
Y.-M. Chiang ◽  
I. Kosacki ◽  
H.L. Tuller

AbstractDense nanocrystalline CeO2-x. of ∼10 nm grain size exhibits enhanced, PO2-dependent electronic conductivity indicative of intrinsic nonstoichiometric behavior under conditions where coarse-grained counterparts are extrinsic. The enthalpy of reduction is lowered by over 2.4 eV per oxygen vacancy. The nanocrystals also exhibit greatly reduced grain boundary resistance, attributed to grain-size-dependent segregation. We propose that interface doping by selected low energy defect sites dominates the defect and transport properties of nanocrystalline ceria, and possibly other nanocrystalline compounds.


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